Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/27871
Change subject: nb/intel/*: Account for cbmem_top alignment ......................................................................
nb/intel/*: Account for cbmem_top alignment
Having cbmem floating between two ram regions is a bad idea and some payloads (e.g. tianocore) even bail out on this. To overcome this issue mark the region between tom and cbmem as uma.
Change-Id: Ifab37b0003f09a680024d5b155ab0bb157920952 Signed-off-by: Arthur Heymans arthur@aheymans.xyz --- M src/northbridge/intel/gm45/northbridge.c M src/northbridge/intel/i945/northbridge.c M src/northbridge/intel/pineview/northbridge.c M src/northbridge/intel/x4x/northbridge.c 4 files changed, 49 insertions(+), 4 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/71/27871/1
diff --git a/src/northbridge/intel/gm45/northbridge.c b/src/northbridge/intel/gm45/northbridge.c index e14f843..d946553 100644 --- a/src/northbridge/intel/gm45/northbridge.c +++ b/src/northbridge/intel/gm45/northbridge.c @@ -13,6 +13,7 @@ * GNU General Public License for more details. */
+#include <cbmem.h> #include <console/console.h> #include <arch/io.h> #include <stdint.h> @@ -72,7 +73,7 @@ static void mch_domain_read_resources(struct device *dev) { u64 tom, touud; - u32 tomk, tolud, uma_sizek = 0; + u32 tomk, tolud, uma_sizek = 0, delta_cbmem; u32 pcie_config_base, pcie_config_size;
/* Total Memory 2GB example: @@ -138,6 +139,15 @@ tomk -= tseg_sizek; uma_sizek += tseg_sizek;
+ /* cbmem_top can be shifted downwards due to aligment. + Mark the region between cbmem_top and tomk as unusable */ + delta_cbmem = tomk - ((uint32_t)cbmem_top() >> 10); + tomk -= delta_cbmem; + uma_sizek += delta_cbmem; + + printk(BIOS_DEBUG, "Unused RAM between cbmem_top and TOM: 0x%xK\n", + delta_cbmem); + printk(BIOS_INFO, "Available memory below 4GB: %uM\n", tomk >> 10);
/* Report the memory regions */ diff --git a/src/northbridge/intel/i945/northbridge.c b/src/northbridge/intel/i945/northbridge.c index d3539b8..b6e1515 100644 --- a/src/northbridge/intel/i945/northbridge.c +++ b/src/northbridge/intel/i945/northbridge.c @@ -13,6 +13,7 @@ * GNU General Public License for more details. */
+#include <cbmem.h> #include <console/console.h> #include <arch/io.h> #include <stdint.h> @@ -62,7 +63,7 @@ uint32_t pci_tolm, tseg_sizek; uint8_t tolud; uint16_t reg16; - unsigned long long tomk, tomk_stolen; + unsigned long long tomk, tomk_stolen, cbmem_topk, delta_cbmem; uint64_t uma_memory_base = 0, uma_memory_size = 0; uint64_t tseg_memory_base = 0, tseg_memory_size = 0;
@@ -102,6 +103,17 @@ tseg_memory_base = tomk_stolen * 1024ULL; tseg_memory_size = tseg_sizek * 1024ULL;
+ /* cbmem_top can be shifted downwards due to aligment. + Mark the region between cbmem_top and tomk as unusable */ + cbmem_topk = ((uint32_t)cbmem_top() >> 10); + delta_cbmem = tomk_stolen - cbmem_topk; + tomk_stolen -= delta_cbmem; + uma_sizek += delta_cbmem; + + printk(BIOS_DEBUG, "Unused RAM between cbmem_top and TOM: 0x%xK\n", + delta_cbmem); + + /* The following needs to be 2 lines, otherwise the second * number is always 0 */ @@ -113,6 +125,7 @@ ram_resource(dev, 4, 768, (tomk - 768)); uma_resource(dev, 5, uma_memory_base >> 10, uma_memory_size >> 10); mmio_resource(dev, 6, tseg_memory_base >> 10, tseg_memory_size >> 10); + uma_resource(dev, 7, cbmem_topk, delta_cbmem);
assign_resources(dev->link_list); } diff --git a/src/northbridge/intel/pineview/northbridge.c b/src/northbridge/intel/pineview/northbridge.c index 4775b15..0c04b35 100644 --- a/src/northbridge/intel/pineview/northbridge.c +++ b/src/northbridge/intel/pineview/northbridge.c @@ -14,6 +14,7 @@ * GNU General Public License for more details. */
+#include <cbmem.h> #include <console/console.h> #include <arch/io.h> #include <stdint.h> @@ -55,7 +56,7 @@ { u64 tom, touud; u32 tomk, tolud, tseg_sizek; - u32 pcie_config_base, pcie_config_size; + u32 pcie_config_base, pcie_config_size, delta_cbmem; u16 index; const u32 top32memk = 4 * (GiB / KiB);
@@ -100,6 +101,17 @@ /* Subtract TSEG size */ tseg_sizek = gtt_basek - tseg_basek; tomk -= tseg_sizek; + printk(BIOS_DEBUG, "TSEG decoded, subtracting %dM\n", tseg_sizek >> 10); + + /* cbmem_top can be shifted downwards due to aligment. + Mark the region between cbmem_top and tomk as unusable */ + delta_cbmem = tomk - ((uint32_t)cbmem_top() >> 10); + tomk -= delta_cbmem; + uma_sizek += delta_cbmem; + + printk(BIOS_DEBUG, "Unused RAM between cbmem_top and TOMK: 0x%xK\n", + delta_cbmem); +
/* Report the memory regions */ ram_resource(dev, index++, 0, 640); diff --git a/src/northbridge/intel/x4x/northbridge.c b/src/northbridge/intel/x4x/northbridge.c index d1926b2..aba5c54 100644 --- a/src/northbridge/intel/x4x/northbridge.c +++ b/src/northbridge/intel/x4x/northbridge.c @@ -14,6 +14,7 @@ * GNU General Public License for more details. */
+#include <cbmem.h> #include <console/console.h> #include <arch/io.h> #include <stdint.h> @@ -35,7 +36,7 @@ { u8 index, reg8; u64 tom, touud; - u32 tomk, tseg_sizek = 0, tolud; + u32 tomk, tseg_sizek = 0, tolud, delta_cbmem; u32 pcie_config_base, pcie_config_size; u32 uma_sizek = 0;
@@ -100,6 +101,15 @@
printk(BIOS_DEBUG, "%dM\n", tseg_sizek >> 10);
+ /* cbmem_top can be shifted downwards due to aligment. + Mark the region between cbmem_top and tomk as unusable */ + delta_cbmem = tomk - ((uint32_t)cbmem_top() >> 10); + tomk -= delta_cbmem; + uma_sizek += delta_cbmem; + + printk(BIOS_DEBUG, "Unused RAM between cbmem_top and TOM: 0x%xK\n", + delta_cbmem); + printk(BIOS_INFO, "Available memory below 4GB: %uM\n", tomk >> 10);
/* Report the memory regions */