Hello Nico Huber,
I'd like you to do a code review. Please visit
https://review.coreboot.org/c/coreboot/+/39828
to review the following change.
Change subject: sb/intel/bd82x6x: Add legacy mode support to SATA ......................................................................
sb/intel/bd82x6x: Add legacy mode support to SATA
Legacy mode is supposed to help with IDE controller drivers that don't know Intel's "native" IDE interface. We extend the `sata_mode` NVRAM variable to provide the following choices:
* 0 "AHCI" - AHCI interface * 1 "Compatible" - Intel's "native" interface * 2 "Legacy" - Legacy interface
Change-Id: I0e7a4befa02772f620602fa2a92c3583895d4d1c Signed-off-by: Nico Huber nico.huber@secunet.com --- M src/southbridge/intel/bd82x6x/sata.c 1 file changed, 7 insertions(+), 4 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/28/39828/1
diff --git a/src/southbridge/intel/bd82x6x/sata.c b/src/southbridge/intel/bd82x6x/sata.c index ba3630a..0f7a042 100644 --- a/src/southbridge/intel/bd82x6x/sata.c +++ b/src/southbridge/intel/bd82x6x/sata.c @@ -138,10 +138,13 @@ reg16 &= ~PCI_COMMAND_MEMORY; pci_write_config16(dev, PCI_COMMAND, reg16);
- /* Native mode capable on both primary and secondary (0xa) - * or'ed with enabled (0x50) = 0xf - */ - pci_write_config8(dev, 0x09, 0x8f); + if (sata_mode == 1) { + /* Native mode on both primary and secondary. */ + pci_or_config8(dev, 0x09, 0x05); + } else { + /* Legacy mode on both primary and secondary. */ + pci_update_config8(dev, 0x09, ~0x05, 0x00); + }
/* Set Interrupt Line */ /* Interrupt Pin is set by D31IP.PIP */