[coreboot-gerrit] Change in coreboot[master]: arch/x86: Remove WB attribute from 0..CACHE_TMP_RAMTOP

[Kyösti Mälkki (Code Review)]

Hello Aaron Durbin, Subrata Banik, Arthur Heymans, Kane Chen, Tim Wawrzynczak, Shelley Chen, David Wu, build bot (Jenkins), Furquan Shaikh,

I'd like you to reexamine a change. Please visit

https://review.coreboot.org/c/coreboot/+/35161

to look at the new patch set (#2).

Change subject: arch/x86: Remove WB attribute from 0..CACHE_TMP_RAMTOP
......................................................................

arch/x86: Remove WB attribute from 0..CACHE_TMP_RAMTOP

Platforms using postcar are with RELOCATABLE_RAMSTAGE=y. They
don't benefit from having low-memory set as writeback-cacheable.

This also fixes regression from CB:34893 that caused some random
hangs with more recent intel SoCs in ramstage.

BUG=b:140250314

Change-Id: Ia66910a6c85286f5c05823b87d48edc7e4ad9541
Signed-off-by: Kyösti Mälkki 
---
M src/arch/x86/postcar_loader.c
1 file changed, 0 insertions(+), 3 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/61/35161/2