Cliff Huang has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/58101 )
Change subject: lib/spd_bin: Fix for LDDR5 ......................................................................
lib/spd_bin: Fix for LDDR5
Added LDDR5 for the param Fixed SPD name for LDDR5
Signed-off-by: Cliff Huang cliff.huang@intel.com Change-Id: I52ecf24a313d4cbdd0859c623533630c6a6c3713 --- M 3rdparty/blobs M 3rdparty/fsp M src/lib/spd_bin.c 3 files changed, 4 insertions(+), 2 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/01/58101/1
diff --git a/3rdparty/blobs b/3rdparty/blobs index f388b67..8c4e2c8 160000 --- a/3rdparty/blobs +++ b/3rdparty/blobs @@ -1 +1 @@ -Subproject commit f388b6794e6f1f93b847de353f5eab8ba3e3b328 +Subproject commit 8c4e2c83362c48154d954aa657b805e0681977b0 diff --git a/3rdparty/fsp b/3rdparty/fsp index 10eae55..cc17338 160000 --- a/3rdparty/fsp +++ b/3rdparty/fsp @@ -1 +1 @@ -Subproject commit 10eae55b8eb0febfa2dfabf4017701b072866170 +Subproject commit cc173384ec4152cde81020da88a2f6cf9c6edfac diff --git a/src/lib/spd_bin.c b/src/lib/spd_bin.c index 865f16c..9c8681e 100644 --- a/src/lib/spd_bin.c +++ b/src/lib/spd_bin.c @@ -34,6 +34,7 @@ case SPD_DRAM_LPDDR3_JEDEC: case SPD_DRAM_DDR4: case SPD_DRAM_DDR5: + case SPD_DRAM_LPDDR5: case SPD_DRAM_LPDDR4: case SPD_DRAM_LPDDR4X: return true; @@ -165,6 +166,7 @@ case SPD_DRAM_LPDDR3_JEDEC: case SPD_DRAM_DDR4: case SPD_DRAM_DDR5: + case SPD_DRAM_LPDDR5: case SPD_DRAM_LPDDR4: case SPD_DRAM_LPDDR4X: *spd_name = (const char *) &spd[DDR4_SPD_PART_OFF];