Attention is currently required from: Alicja Michalska, Michał Żygowski, Nicholas Chin, Paul Menzel.
Felix Singer has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/80853?usp=email )
Change subject: mb/erying: Add Erying Polestar G613 Pro (TGL-H) ......................................................................
Patch Set 6:
(12 comments)
File src/mainboard/erying/tgl/devicetree.cb:
https://review.coreboot.org/c/coreboot/+/80853/comment/814f1db9_40ebca74 : PS6, Line 19: register "SkipExtGfxScan" = "0" Set to 0, which is the default. Remove.
https://review.coreboot.org/c/coreboot/+/80853/comment/205b1d1d_93a5330f : PS6, Line 21: register "s0ix_enable" = "0" Set to 0, which is the default. Remove.
https://review.coreboot.org/c/coreboot/+/80853/comment/81f5ab85_5b72b377 : PS6, Line 23: # Actual device tree begins here: Seems superfluous.
https://review.coreboot.org/c/coreboot/+/80853/comment/b3defb02_477b8403 : PS6, Line 26: device ref system_agent on end System agent is enabled by default, remove.
https://review.coreboot.org/c/coreboot/+/80853/comment/2741e1f5_75d692b9 : PS6, Line 56: [0] = USB2_PORT_MID(OC0), /* Rear, bottom right */ : [1] = USB2_PORT_MID(OC0), /* Rear, bottom left */ : [2] = USB2_PORT_MID(OC2), /* NIC left */ : [3] = USB2_PORT_MID(OC2), /* NIC right */ : [4] = USB2_PORT_MID(OC2), /* Front Panel 1 */ : [5] = USB2_PORT_MID(OC2), /* Front Panel 2 */ : [8] = USB2_PORT_MID(OC0), /* Front Panel 1 (USB3) */ : [9] = USB2_PORT_MID(OC0), /* Front Panel 2 (USB3) */ : [10] = USB2_PORT_MID(OC0), /* Rear, top left */ : Add one more tab
https://review.coreboot.org/c/coreboot/+/80853/comment/7e236ed9_5b0dea1f : PS6, Line 69: [0] = USB3_PORT_DEFAULT(OC0), /* Rear, bottom right */ : [1] = USB3_PORT_DEFAULT(OC0), /* Rear, bottom left */ : [2] = USB3_PORT_DEFAULT(OC0), /* Front Panel 1 */ : [3] = USB3_PORT_DEFAULT(OC0), /* Front Panel 2 */ : [4] = USB3_PORT_DEFAULT(OC0), /* Rear, top left */ : Add one more tab
https://review.coreboot.org/c/coreboot/+/80853/comment/4329a299_202bc045 : PS6, Line 81: register "SataMode" = "0" AHCI is the default, remove.
File src/mainboard/erying/tgl/ramstage.c:
PS6: Same as with romstage_fsp_params.c
File src/mainboard/erying/tgl/romstage_fsp_params.c:
PS6: I marked a few options which seemed obvious to me. Please have a look at the SoC code and the FSP defaults. Some of them might not be needed since your configuration might correspond to the defaults and there might be an option for others.
https://review.coreboot.org/c/coreboot/+/80853/comment/ff511e1c_0cf08002 : PS6, Line 25: mupd->FspmConfig.HyperThreading = 1; Remove. This is hooked up to the runtime setting `hyper_threading` and also to Kconfig.
https://review.coreboot.org/c/coreboot/+/80853/comment/41ee9f09_59d04c8f : PS6, Line 58: mupd->FspmConfig.VmxEnable = 1; Remove. This option is hooked up to the `ENABLE_VMX` Kconfig option.
https://review.coreboot.org/c/coreboot/+/80853/comment/58eba175_78bf60b9 : PS6, Line 59: mupd->FspmConfig.SmbusEnable = 1; Remove. That option is hooked up to the devicetree and it's enabled there.