Brandon Breitenstein has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38737 )
Change subject: soc/tigerlake: Update FSP UPDs to turn on USB4/TBT ......................................................................
Patch Set 2:
(4 comments)
https://review.coreboot.org/c/coreboot/+/38737/1/src/soc/intel/tigerlake/fsp... File src/soc/intel/tigerlake/fsp_params_tgl.c:
https://review.coreboot.org/c/coreboot/+/38737/1/src/soc/intel/tigerlake/fsp... PS1, Line 139: 4
ARRAY_SIZE()
Done
https://review.coreboot.org/c/coreboot/+/38737/1/src/soc/intel/tigerlake/fsp... PS1, Line 140: params->ITbtPcieRootPortEn[i] = 1;
This should be a devicetree config option that we can associate with the device itself. […]
Done
https://review.coreboot.org/c/coreboot/+/38737/1/src/soc/intel/tigerlake/rom... File src/soc/intel/tigerlake/romstage/fsp_params_tgl.c:
https://review.coreboot.org/c/coreboot/+/38737/1/src/soc/intel/tigerlake/rom... PS1, Line 134: m_cfg->TcssItbtPcie0En = 1;
Same comment as my other one relating to driving these values from devicetree.
Done
https://review.coreboot.org/c/coreboot/+/38737/1/src/soc/intel/tigerlake/rom... PS1, Line 137: m_cfg->TcssItbtPcie3En = 1;
Why does the information need to be in two places?
This is for Tcss Config and the Soc one is for root port config