Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/34894 )
Change subject: soc/intel: Move fill_postcar_frame to memmap.c ......................................................................
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Do you see this code working ? when we tries to run marking postcar region as cache WB?
refer the comments here https://review.coreboot.org/c/coreboot/+/34805 We are working to make this work (yesterday Patrick R helped to run on his KBL machine, last 3 days me and Aaron are debugging this issue). recommend you to follow this CL and share your opinion rather just trying to do duplicate stuff.
This is orthogonal work to keep some consistency across platforms, wrt. where certain functions are implemented. At the end of the day this will help you create the API you need to apply WB/WT/WC MTRRs at end of romstage, should you find a stable solution for the skip-postcar approach.
yes, we have root causes why WB can't work vs WP/WC works and we have almost done with implementation where WB marking as intermediate postcar caching is able to boot the system. Also it can directly load ramstage by skipping postcar approach,
I really appreciate your https://review.coreboot.org/c/coreboot/+/34893/1 CL, this is something we wish to create and call as Intel Common code 2.0 approach where all soc will use common stage files like you have done here. We should talk after finishing this approach.