Attention is currently required from: Nico Huber, Tim Wawrzynczak, Angel Pons, Subrata Banik, Michael Niewöhner, EricR Lai.
Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/48340 )
Change subject: soc/intel/alderlake: Refactor PCIE port config
......................................................................
Patch Set 70: Code-Review+1
(2 comments)
Patchset:
PS70:
Change looks okay. Waiting for reviews from others on the CL.
File src/soc/intel/alderlake/romstage/fsp_params.c:
https://review.coreboot.org/c/coreboot/+/48340/comment/981dbf15_80279692
PS65, Line 151: /* Don't disable SRC CLK from external clock chip on ADL-P */
Maybe external CLK chip is control by GPIO maybe? Or it always running.
But, FSP has no knowledge of the external chip. The UPDs here are specifically for the clocks that are under the control of SoC.
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