Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38010 )
Change subject: nb/intel/sandybridge: add and use more MCHBAR register defines ......................................................................
Patch Set 1:
(12 comments)
https://review.coreboot.org/c/coreboot/+/38010/1/src/northbridge/intel/sandy... File src/northbridge/intel/sandybridge/raminit_common.c:
https://review.coreboot.org/c/coreboot/+/38010/1/src/northbridge/intel/sandy... PS1, Line 248: 0x400c
TC_OTHP_C0
Ack
https://review.coreboot.org/c/coreboot/+/38010/1/src/northbridge/intel/sandy... PS1, Line 362: 0x5014
MAD_ZR
Ack
https://review.coreboot.org/c/coreboot/+/38010/1/src/northbridge/intel/sandy... PS1, Line 988: 0xc14
GDCRCKPICODE_C0
Ack
https://review.coreboot.org/c/coreboot/+/38010/1/src/northbridge/intel/sandy... PS1, Line 989: 0xc18
GDCRCKLOGICDELAY_C0
Ack
https://review.coreboot.org/c/coreboot/+/38010/1/src/northbridge/intel/sandy... PS1, Line 1067: 0x4024
SC_ROUNDT_LAT_C0
Ack
https://review.coreboot.org/c/coreboot/+/38010/1/src/northbridge/intel/sandy... PS1, Line 1073: 428c
MCHBAR32(0x428C) == MCHBAR32(IOSAV_STATUS_C0)
Ack
https://review.coreboot.org/c/coreboot/+/38010/1/src/northbridge/intel/sandy... PS1, Line 3162: 0x4384
PM_CMD_PWR_C0
Ack
https://review.coreboot.org/c/coreboot/+/38010/1/src/northbridge/intel/sandy... PS1, Line 3174: 0x5030
MC_INIT_STATE_G
Ack
https://review.coreboot.org/c/coreboot/+/38010/1/src/northbridge/intel/sandy... PS1, Line 3176: 0x5f18
BANDTIMERS
Ack
https://review.coreboot.org/c/coreboot/+/38010/1/src/northbridge/intel/sandy... PS1, Line 3182: 0x4290
TC_ZQCAL_C0
Ack
https://review.coreboot.org/c/coreboot/+/38010/1/src/northbridge/intel/sandy... File src/northbridge/intel/sandybridge/sandybridge.h:
https://review.coreboot.org/c/coreboot/+/38010/1/src/northbridge/intel/sandy... PS1, Line 135: PM_PDWN_Config
CB:38028
Done
https://review.coreboot.org/c/coreboot/+/38010/1/src/northbridge/intel/sandy... PS1, Line 141: 0x5d14
I thought this was 0x5d10 ?
Will revise