Mathew King has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/36045 )
Change subject: mb/g/drallion: Enable privacy screen on Drallion variant ......................................................................
mb/g/drallion: Enable privacy screen on Drallion variant
Enable ACPI methods to control privacy screen on Drallion devices. Drallion devices may not have a privacy screen and it is up to the EC to determine if the privacy screen is present on the system.
BUG=b:142656363 TEST=emerge-drallion coreboot chromeos-bootimage
Change-Id: I79d02bb1b25f0deb49ae4bb852b7ed8c21fd31c7 Signed-off-by: Mathew King mathewk@chromium.org --- M src/mainboard/google/drallion/Kconfig M src/mainboard/google/drallion/dsdt.asl M src/mainboard/google/drallion/variants/drallion/devicetree.cb M src/mainboard/google/drallion/variants/drallion/include/variant/ec.h 4 files changed, 18 insertions(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/45/36045/1
diff --git a/src/mainboard/google/drallion/Kconfig b/src/mainboard/google/drallion/Kconfig index 256f8cb..1de5ea5 100644 --- a/src/mainboard/google/drallion/Kconfig +++ b/src/mainboard/google/drallion/Kconfig @@ -2,6 +2,7 @@ config BOARD_GOOGLE_BASEBOARD_DRALLION def_bool n select BOARD_ROMSIZE_KB_32768 + select DRIVERS_GENERIC_GFX if BOARD_GOOGLE_DRALLION select DRIVERS_I2C_GENERIC select DRIVERS_I2C_HID select DRIVERS_INTEL_ISH diff --git a/src/mainboard/google/drallion/dsdt.asl b/src/mainboard/google/drallion/dsdt.asl index 2568800..5c2a5c9 100644 --- a/src/mainboard/google/drallion/dsdt.asl +++ b/src/mainboard/google/drallion/dsdt.asl @@ -39,6 +39,7 @@ { #include <soc/intel/cannonlake/acpi/northbridge.asl> #include <soc/intel/cannonlake/acpi/southbridge.asl> + #include <soc/intel/cannonlake/acpi/gfx.asl> } /* Per board variant mainboard hooks. */ #include <variant/acpi/mainboard.asl> diff --git a/src/mainboard/google/drallion/variants/drallion/devicetree.cb b/src/mainboard/google/drallion/variants/drallion/devicetree.cb index 1f628d6..184ab63 100644 --- a/src/mainboard/google/drallion/variants/drallion/devicetree.cb +++ b/src/mainboard/google/drallion/variants/drallion/devicetree.cb @@ -222,7 +222,19 @@ end device domain 0 on device pci 00.0 on end # Host Bridge - device pci 02.0 on end # Integrated Graphics Device + device pci 02.0 on + chip drivers/generic/gfx + register "device_count" = "1" + register "device[0].name" = ""LCD"" + register "device[0].addr" = "0x0400" + register "device[0].privacy.enabled" = "1" + register "device[0].privacy.detect_function" = ""\_SB.PCI0.LPCB.EC0.GPVD"" + register "device[0].privacy.status_function" = ""\_SB.PCI0.LPCB.EC0.GPVX"" + register "device[0].privacy.enable_function" = ""\_SB.PCI0.LPCB.EC0.EPVX"" + register "device[0].privacy.disable_function" = ""\_SB.PCI0.LPCB.EC0.DPVX"" + device generic 0 on end + end + end # Integrated Graphics Device device pci 04.0 on end # SA Thermal device device pci 12.0 on end # Thermal Subsystem device pci 12.5 off end # UFS SCS diff --git a/src/mainboard/google/drallion/variants/drallion/include/variant/ec.h b/src/mainboard/google/drallion/variants/drallion/include/variant/ec.h index 01a17b5..9cb8ed0 100644 --- a/src/mainboard/google/drallion/variants/drallion/include/variant/ec.h +++ b/src/mainboard/google/drallion/variants/drallion/include/variant/ec.h @@ -31,4 +31,7 @@ /* Enable DPTF */ #define EC_ENABLE_DPTF
+/* Enable Privacy */ +#define EC_ENABLE_PRIVACY + #endif