[coreboot-gerrit] Change in coreboot[master]: soc/amd/picasso: Cleanup legacy UART config

[Felix Held (Code Review)]

Hello build bot (Jenkins), Martin Roth, Rob Barnes,

I'd like you to reexamine a change. Please visit

https://review.coreboot.org/c/coreboot/+/40322

to look at the new patch set (#2).

Change subject: soc/amd/picasso: Cleanup legacy UART config
......................................................................

soc/amd/picasso: Cleanup legacy UART config

Cleaned up configuration of the legacy UART.
Added Kconfig options for the mapping between UART
and legacy I/O decode.

TEST=Manual, boot trembyle, verify UART configured correctly in log.
    serial8250: ttyS3 at I/O 0x2e8 (IRQ = 3, base_baud = 115200) is
    a 16550A
    $ io_write8 0x2e8 97 -> a is output on console

BUG=b:143283592
BUG=b:153675918

Signed-off-by: Rob Barnes 
Change-Id: Id08ff6428d4019303ebb6e44e13aba480cf1fde2
Reviewed-on: https://chromium-review.googlesource.com/2037891
Reviewed-by: Martin Roth 
Tested-by: Martin Roth 
---
M src/soc/amd/picasso/Kconfig
M src/soc/amd/picasso/include/soc/southbridge.h
M src/soc/amd/picasso/southbridge.c
M src/soc/amd/picasso/uart.c
4 files changed, 39 insertions(+), 19 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/22/40322/2