Dtrain Hsu has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/37229 )
Change subject: hatch: Create stryke variant ......................................................................
Patch Set 3:
(7 comments)
https://review.coreboot.org/c/coreboot/+/37229/2/src/mainboard/google/hatch/... File src/mainboard/google/hatch/variants/stryke/Makefile.inc:
https://review.coreboot.org/c/coreboot/+/37229/2/src/mainboard/google/hatch/... PS2, Line 13: SPD_SOURCES = 4G_2400 # 0b000 : SPD_SOURCES += empty_ddr4 # 0b001 : SPD_SOURCES += 8G_2400 # 0b010 : SPD_SOURCES += 8G_2666 # 0b011 : SPD_SOURCES += 16G_2400 # 0b100 : SPD_SOURCES += 16G_2666 # 0b101 : SPD_SOURCES += 8G_3200 # 0b110
The build scripts generate a single file by concatenating the SPD files specified here, in order. […]
schematic: https://partnerissuetracker.corp.google.com/issues/144797616#comment3
https://review.coreboot.org/c/coreboot/+/37229/2/src/mainboard/google/hatch/... File src/mainboard/google/hatch/variants/stryke/gpio.c:
https://review.coreboot.org/c/coreboot/+/37229/2/src/mainboard/google/hatch/... PS2, Line 21: static const struct pad_config gpio_table[] = {
I'm assuming these were taken from the Hatch variant, again no schematics to verify against.
https://partnerissuetracker.corp.google.com/issues/144797616#comment3
https://review.coreboot.org/c/coreboot/+/37229/2/src/mainboard/google/hatch/... File src/mainboard/google/hatch/variants/stryke/include/variant/gpio.h:
https://review.coreboot.org/c/coreboot/+/37229/2/src/mainboard/google/hatch/... PS2, Line 20: /* Copied from baseboard and may need to change for the new variant. */
Very likely that this needs to be changed. I don't have access to any schematics, so I can't check. […]
schematic: https://partnerissuetracker.corp.google.com/issues/144797616#comment3 GPP_F2 is MEM_CH_SEL (0: dual channel, 1: single channel)
https://review.coreboot.org/c/coreboot/+/37229/2/src/mainboard/google/hatch/... File src/mainboard/google/hatch/variants/stryke/overridetree.cb:
https://review.coreboot.org/c/coreboot/+/37229/2/src/mainboard/google/hatch/... PS2, Line 1: chip soc/intel/cannonlake
Done
https://review.coreboot.org/c/coreboot/+/37229/2/src/mainboard/google/hatch/... PS2, Line 3: register "SerialIoDevMode" = "{
Some of these seem to be unused and could be "PchSerialIoDisabled"
Done
https://review.coreboot.org/c/coreboot/+/37229/2/src/mainboard/google/hatch/... PS2, Line 38: .rise_time_ns = 50, : .fall_time_ns = 15,
These will need to be tuned for your board.
Done
https://review.coreboot.org/c/coreboot/+/37229/2/src/mainboard/google/hatch/... PS2, Line 46: .i2c[3] = { : .speed = I2C_SPEED_FAST, : .rise_time_ns = 150, : .fall_time_ns = 150, : },
Looks like I2C3 is disabled in the devicetree? […]
Done