[coreboot-gerrit] Change in coreboot[master]: soc/intel/tigerlake: Add macros and SPD information for DDR4

[Furquan Shaikh (Code Review)]

Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39866 )

Change subject: soc/intel/tigerlake: Add macros and SPD information for DDR4
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Patch Set 11:

(2 comments)

https://review.coreboot.org/c/coreboot/+/39866/11/src/soc/intel/tigerlake/in... 
File src/soc/intel/tigerlake/include/soc/meminit.h:

https://review.coreboot.org/c/coreboot/+/39866/11/src/soc/intel/tigerlake/in... 
PS11, Line 25: s(
> nit: space

Done

https://review.coreboot.org/c/coreboot/+/39866/11/src/soc/intel/tigerlake/in... 
PS11, Line 54: SMBUS
> addr_dimmN or say leave the smbus address as 0?

Woops. Thanks for catching that.