[coreboot-gerrit] Change in coreboot[master]: mb/intel/adlrvp: Add ADL-P romstage mainboard code

[Subrata Banik (Code Review)]

Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/46091 )

Change subject: mb/intel/adlrvp: Add ADL-P romstage mainboard code
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Patch Set 8:

(1 comment)

https://review.coreboot.org/c/coreboot/+/46091/7/src/mainboard/intel/adlrvp/... 
File src/mainboard/intel/adlrvp/variants/adlrvp_p/devicetree.cb:

https://review.coreboot.org/c/coreboot/+/46091/7/src/mainboard/intel/adlrvp/... 
PS7, Line 8: register "SaGv" = "SaGv_Disabled"
> Ah, hrm. […]

I'm totally agree with you Angel, Sagv shouldn't need to manage from MB devicetree as this is more SoC related but the only concern we have in some new MB PO with untested DIMM we have seen recommendation coming from HW team to not enable SaGv and allow it to boot with lower freq scaling hence keeping it in MB. But we can safely move FSI products SaGv into Kconfig and make this practice. May be you can look at CNL/CML/SKL/ICL boards and come up with those changes ?