Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/82067?usp=email )
Change subject: mb/google/brox: Fix the pad reset config for Touchpad interrupt ......................................................................
mb/google/brox: Fix the pad reset config for Touchpad interrupt
Update the pad reset config for Touchpad Interrupt from PLTRST to DEEP so that it can still act as a wake source during S3 suspend.
BUG=b:336398012 TEST=Build Brox BIOS image and boot to OS. Suspend to S3 and wakeup using Trackpad. 246 | 2024-04-25 16:55:18-0700 | ACPI Enter | S3 247 | 2024-04-25 16:55:34-0700 | ACPI Wake | S3 248 | 2024-04-25 16:55:34-0700 | Wake Source | GPE # | 67 249 | 2024-04-25 17:00:38-0700 | ACPI Enter | S3 250 | 2024-04-25 17:00:47-0700 | ACPI Wake | S3 251 | 2024-04-25 17:00:47-0700 | Wake Source | GPE # | 67 Also suspend to S0ix and wakeup using Trackpad.
Change-Id: If1a275e42c6c7ad743eedc9cd3320776008bfd62 Signed-off-by: Karthikeyan Ramasubramanian kramasub@google.com Reviewed-on: https://review.coreboot.org/c/coreboot/+/82067 Tested-by: build bot (Jenkins) no-reply@coreboot.org Reviewed-by: Shelley Chen shchen@google.com --- M src/mainboard/google/brox/variants/baseboard/brox/gpio.c 1 file changed, 1 insertion(+), 1 deletion(-)
Approvals: Shelley Chen: Looks good to me, approved build bot (Jenkins): Verified
diff --git a/src/mainboard/google/brox/variants/baseboard/brox/gpio.c b/src/mainboard/google/brox/variants/baseboard/brox/gpio.c index 3d87bf25..f745851 100644 --- a/src/mainboard/google/brox/variants/baseboard/brox/gpio.c +++ b/src/mainboard/google/brox/variants/baseboard/brox/gpio.c @@ -187,7 +187,7 @@ /* GPP_E2 : THC0_SPI1_IO3 ==> GSC_PCH_INT_ODL */ PAD_CFG_GPI_APIC_LOCK(GPP_E2, NONE, LEVEL, INVERT, LOCK_CONFIG), /* GPP_E3 : [NF1: PROC_GP0 NF6: USB_C_GPP_E3] ==> TCHPAD_INT_ODL */ - PAD_CFG_GPI_IRQ_WAKE(GPP_E3, NONE, PLTRST, LEVEL, INVERT), + PAD_CFG_GPI_IRQ_WAKE(GPP_E3, NONE, DEEP, LEVEL, INVERT), /* GPP_E4 : [NF1: DEVSLP0 NF6: USB_C_GPP_E4 NF7: SRCCLK_OE9#] ==> USB4_BB_RT_FORCE_PWR */ PAD_CFG_GPO(GPP_E4, 1, PLTRST), /* GPP_E5 : [NF1: DEVSLP1 NF6: USB_C_GPP_E5 NF7: SRCCLK_OE6#] ==> SOC_GPP_E5 (NC) */