Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/44183 )
Change subject: security/intel/txt: Fix variable MTRR handling ......................................................................
security/intel/txt: Fix variable MTRR handling
The MSR macros were treated as memory addresses and the loops had off-by-one errors. This resulted in a hang right before GETSEC.
Tested on Asrock B85M Pro4, ACM complains about the missing TPM.
Change-Id: Ib5d23cf9885401f3ec69b0f14cea7bad77eee19a Signed-off-by: Angel Pons th3fanbus@gmail.com --- M src/security/intel/txt/getsec_enteraccs.S 1 file changed, 23 insertions(+), 18 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/83/44183/1
diff --git a/src/security/intel/txt/getsec_enteraccs.S b/src/security/intel/txt/getsec_enteraccs.S index 0dd5237..fffb6b0 100644 --- a/src/security/intel/txt/getsec_enteraccs.S +++ b/src/security/intel/txt/getsec_enteraccs.S @@ -31,7 +31,7 @@ .macro PUSH_VAR_MTRR movl %ebx, %ecx shll %ecx - addl MTRR_PHYS_BASE(0), %ecx + addl $(MTRR_PHYS_BASE(0)), %ecx rdmsr push %eax push %edx @@ -44,7 +44,7 @@ .macro POP_VAR_MTRR movl %ebx, %ecx shll %ecx - addl MTRR_PHYS_MASK(0), %ecx + addl $(MTRR_PHYS_MASK(0)), %ecx pop %edx pop %eax wrmsr @@ -54,19 +54,6 @@ wrmsr .endm
-.macro CLEAR_VAR_MTRR - movl %ebx, %ecx - shll %ecx - addl MTRR_PHYS_BASE(0), %ecx - xorl %edx, %edx - xorl %eax, %eax - wrmsr - incl %ecx /* MTRR_PHYS_MASK */ - xorl %edx, %edx - xorl %eax, %eax - wrmsr -.endm - .align 4 .text
@@ -125,7 +112,7 @@ rdmsr andl $(0xff), %eax cmp %ebx, %eax - jge body_push_var_mtrrs + jg body_push_var_mtrrs
/* * Disable cache. @@ -168,9 +155,22 @@ andl $(0xff), %eax movl %eax, %ebx
+ xorl %eax, %eax + xorl %edx, %edx + + jmp cond_clear_var_mtrrs + body_clear_var_mtrrs:
- CLEAR_VAR_MTRR + movl %ebx, %ecx + shll %ecx + addl $(MTRR_PHYS_BASE(0)), %ecx + wrmsr + incl %ecx /* MTRR_PHYS_MASK */ + wrmsr + +cond_clear_var_mtrrs: + decl %ebx jnz body_clear_var_mtrrs
@@ -274,9 +274,14 @@ andl $(0xff), %eax movl %eax, %ebx
+ jmp cond_pop_var_mtrrs + body_pop_var_mtrrs:
POP_VAR_MTRR + +cond_pop_var_mtrrs: + decl %ebx jnz body_pop_var_mtrrs
@@ -301,7 +306,7 @@ /* Enable cache */ movl %cr0, %eax andl $(~(CR0_CD | CR0_NW)), %eax - movl %eax, %cr0 + movl %eax, %cr0
/* Pop GDT */ addl $8, %esp