[coreboot-gerrit] Change in coreboot[master]: drivers/genesyslogic/gl9755: Adjust L1 exit latency to enable ASPM

[Duncan Laurie (Code Review)]

Hello build bot (Jenkins),

I'd like you to reexamine a change. Please visit

https://review.coreboot.org/c/coreboot/+/47682

to look at the new patch set (#2).

Change subject: drivers/genesyslogic/gl9755: Adjust L1 exit latency to enable ASPM
......................................................................

drivers/genesyslogic/gl9755: Adjust L1 exit latency to enable ASPM

Configure the CFG2 register to set the latency to <64us in order
to ensure the L1 exit latency is consistent across devices and that
L1 ASPM is always enabled.

This moves the setup code from device init to device enable so it
executes before coreboot does ASPM configuration, and removes the
call to pci_dev_init() as that is just for VGA Option ROMs.

BUG=b:173207454
TEST=Verify the device and link capability and control for L1:
DevCap: Latency L1 <64us
LnkCap: Latency L1 <64us
LnkCtl: ASPM L1 Enabled

Signed-off-by: Duncan Laurie 
Change-Id: Ie2b85a6697f164fbe4f84d8cd5acb2b5911ca7a9
---
M src/drivers/genesyslogic/gl9755/gl9755.c
M src/drivers/genesyslogic/gl9755/gl9755.h
2 files changed, 21 insertions(+), 4 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/82/47682/2