[coreboot-gerrit] Change in coreboot[master]: soc/intel/tigerlake: add Rcomp data structure

[Srinidhi N Kaushik (Code Review)]

Srinidhi N Kaushik has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/39040 )

Change subject: soc/intel/tigerlake: add Rcomp data structure
......................................................................

soc/intel/tigerlake: add Rcomp data structure

Add Rcomp data structure in meminit to support updating rcomp resistor and target
values for DDR4 support.

BUG=none
BRANCH=none
TEST= build tglrvp flash and boot to kernel

Signed-off-by: Srinidhi N Kaushik 
Change-Id: I3858cc56c838862fc61123c8b7dba11dbc40983c
---
M src/soc/intel/tigerlake/include/soc/meminit_tgl.h
1 file changed, 11 insertions(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/40/39040/1

diff --git a/src/soc/intel/tigerlake/include/soc/meminit_tgl.h b/src/soc/intel/tigerlake/include/soc/meminit_tgl.h
old mode 100644
new mode 100755
index dd05418..c093304
--- a/src/soc/intel/tigerlake/include/soc/meminit_tgl.h
+++ b/src/soc/intel/tigerlake/include/soc/meminit_tgl.h
@@ -17,6 +17,7 @@
 #define BITS_PER_BYTE		8
 #define DQS_PER_CHANNEL		2
 #define NUM_CHANNELS		8
+#define NUM_RCOMP_TARGETS	5

struct spd_by_pointer {
    size_t spd_data_len;
@@ -61,6 +62,16 @@
    uint8_t ect;
 };

+/* Rcomp configuration information */
+struct rcomp_cfg {
+	/* Rcomp Resistor */
+	uint16_t rcomp_resistor;
+
+	/* Rcomp Target */
+	uint16_t rcomp_target[NUM_RCOMP_TARGETS];
+
+};
+
 /* Initialize default memory configurations for dimm0-only lpddr4x */
 void meminit_lpddr4x_dimm0(FSP_M_CONFIG *mem_cfg,
    		   const struct mb_lpddr4x_cfg *board_cfg,