[coreboot-gerrit] Change in ...coreboot[master]: southbridge/intel/fsp_rangeley: Fixing wrong parameters passed to outw

[Name of user not set (Code Review)]

[e-mail] has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/32842

Change subject: southbridge/intel/fsp_rangeley: Fixing wrong parameters passed to outw
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southbridge/intel/fsp_rangeley: Fixing wrong parameters passed to outw

outw takes (value, addr) not (addr, value)

Change-Id: I6c00413ce9b9b6a3d5691d71ade2b12b08538622
---
M src/southbridge/intel/fsp_rangeley/early_init.c
1 file changed, 2 insertions(+), 2 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/42/32842/1

diff --git a/src/southbridge/intel/fsp_rangeley/early_init.c b/src/southbridge/intel/fsp_rangeley/early_init.c
index 32e3bb5..230f6e1 100644
--- a/src/southbridge/intel/fsp_rangeley/early_init.c
+++ b/src/southbridge/intel/fsp_rangeley/early_init.c
@@ -40,8 +40,8 @@
    /* Disable the watchdog reboot and turn off the watchdog timer */
    write8((void *)(DEFAULT_PBASE + PMC_CFG),
           read8((void *)(DEFAULT_PBASE + PMC_CFG)) | NO_REBOOT);	// disable reboot on timer trigger
-	outw(DEFAULT_ABASE + TCO1_CNT, inw(DEFAULT_ABASE + TCO1_CNT) |
-		TCO_TMR_HALT);	// disable watchdog timer
+	outw( inw(DEFAULT_ABASE + TCO1_CNT) | TCO_TMR_HALT,
+		DEFAULT_ABASE + TCO1_CNT);	// disable watchdog timer

printk(BIOS_DEBUG, " done.\n");