Lijian Zhao has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/32367
Change subject: mb/google/sarien: Fix s5 touchscreen power leakage ......................................................................
mb/google/sarien: Fix s5 touchscreen power leakage
Leakage power is observed from 3V_TSP_S0_FUSE during S5. To avoid leakage power, GPP_E7 needs to be turned off before S5 entry.
BUG=b:129899315 TEST=Measure leakage power in S5 from both Arcada and Sarien
Signed-off-by: Lijian Zhao lijian.zhao@intel.com Change-Id: Ie4229477b7149c0a75f4a8c6c7c453a37cc1c78c --- M src/mainboard/google/sarien/dsdt.asl A src/mainboard/google/sarien/variants/arcada/include/variant/acpi/mainboard.asl A src/mainboard/google/sarien/variants/sarien/include/variant/acpi/mainboard.asl 3 files changed, 52 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/67/32367/1
diff --git a/src/mainboard/google/sarien/dsdt.asl b/src/mainboard/google/sarien/dsdt.asl index e5b0cca..09ffd91 100644 --- a/src/mainboard/google/sarien/dsdt.asl +++ b/src/mainboard/google/sarien/dsdt.asl @@ -39,6 +39,8 @@ { #include <soc/intel/cannonlake/acpi/northbridge.asl> #include <soc/intel/cannonlake/acpi/southbridge.asl> + /* Per board variant mainboard hooks. */ + #include <variant/acpi/mainboard.asl> } }
diff --git a/src/mainboard/google/sarien/variants/arcada/include/variant/acpi/mainboard.asl b/src/mainboard/google/sarien/variants/arcada/include/variant/acpi/mainboard.asl new file mode 100644 index 0000000..2d6260b --- /dev/null +++ b/src/mainboard/google/sarien/variants/arcada/include/variant/acpi/mainboard.asl @@ -0,0 +1,25 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2019 Intel Corp. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#define TS_PD GPP_E7 + +/* Method called from _PTS prior to enter sleep state */ +Method(MPTS, 1) { + /* Before enter S5 soft off state */ + If (Arg0 == 5) { + /* Clear touch screen pd pin to avoid leakage */ + CTXS(TS_PD) + } /*S5 soft off state*/ +} diff --git a/src/mainboard/google/sarien/variants/sarien/include/variant/acpi/mainboard.asl b/src/mainboard/google/sarien/variants/sarien/include/variant/acpi/mainboard.asl new file mode 100644 index 0000000..2d6260b --- /dev/null +++ b/src/mainboard/google/sarien/variants/sarien/include/variant/acpi/mainboard.asl @@ -0,0 +1,25 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2019 Intel Corp. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#define TS_PD GPP_E7 + +/* Method called from _PTS prior to enter sleep state */ +Method(MPTS, 1) { + /* Before enter S5 soft off state */ + If (Arg0 == 5) { + /* Clear touch screen pd pin to avoid leakage */ + CTXS(TS_PD) + } /*S5 soft off state*/ +}