Caveh Jalali has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39459 )
Change subject: soc/intel/tigerlake: Configure IOM_TYPEC_SW_CONFIGURATUON_3
......................................................................
Patch Set 2:
(1 comment)
https://review.coreboot.org/c/coreboot/+/39459/2//COMMIT_MSG
Commit Message:
https://review.coreboot.org/c/coreboot/+/39459/2//COMMIT_MSG@10
PS2, Line 10: port 2
I will update the commit message this is able to control all the type-c port retimer enabled or disa […]
so, is this a global control bit that applies to all the ports as a group? wouldn't we need to control the retimer on each port indepentlenly to match the requirements of the system?
--
To view, visit
https://review.coreboot.org/c/coreboot/+/39459
To unsubscribe, or for help writing mail filters, visit
https://review.coreboot.org/settings
Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Change-Id: Iae356113cbdc72983f800060b1ebebe3c66b9daf
Gerrit-Change-Number: 39459
Gerrit-PatchSet: 2
Gerrit-Owner: Brandon Breitenstein
brandon.breitenstein@intel.com
Gerrit-Reviewer: Caveh Jalali
caveh@chromium.org
Gerrit-Reviewer: Furquan Shaikh
furquan@google.com
Gerrit-Reviewer: Nick Vaccaro
nvaccaro@google.com
Gerrit-Reviewer: Patrick Rudolph
siro@das-labor.org
Gerrit-Reviewer: Wonkyu Kim
wonkyu.kim@intel.com
Gerrit-Reviewer: build bot (Jenkins)
no-reply@coreboot.org
Gerrit-CC: Patrick Georgi
pgeorgi@google.com
Gerrit-Comment-Date: Thu, 12 Mar 2020 23:58:20 +0000
Gerrit-HasComments: Yes
Gerrit-Has-Labels: No
Comment-In-Reply-To: Caveh Jalali
caveh@chromium.org
Comment-In-Reply-To: Brandon Breitenstein
brandon.breitenstein@intel.com
Gerrit-MessageType: comment