[coreboot-gerrit] Change in coreboot[master]: post_code: replace postcode values with their respective defined cons...

[Sindhoor Tilak (Code Review)]

Hello build bot (Jenkins), Damien Zammit, Lee Leahy, Angel Pons, Huang Jin, Andrey Petrov, Patrick Rudolph,

I'd like you to reexamine a change. Please visit

https://review.coreboot.org/c/coreboot/+/42503

to look at the new patch set (#4).

Change subject: post_code: replace postcode values with their respective defined constants
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post_code: replace postcode values with their respective defined constants

* Replace existing post_code call values with their defined constants
* Reorganize certain post_code calls to match their respective defines
* Updated define values reflect the newer changes to post_codes.h

Signed-off-by: Sindhoor Tilak 
Change-Id: If32f43104a829bd1db0d5f5340cc94bf0c717c39
---
M src/arch/x86/postcar_loader.c
M src/arch/x86/tables.c
M src/cpu/intel/car/core2/cache_as_ram.S
M src/cpu/intel/car/non-evict/cache_as_ram.S
M src/cpu/intel/car/p3/cache_as_ram.S
M src/cpu/intel/car/p4-netburst/cache_as_ram.S
M src/cpu/intel/haswell/romstage.c
M src/cpu/x86/mtrr/mtrr.c
M src/device/pci_device.c
M src/drivers/intel/fsp1_1/fsp_util.c
M src/drivers/intel/fsp1_1/romstage.c
M src/lib/ramtest.c
M src/northbridge/intel/sandybridge/raminit.c
M src/northbridge/intel/sandybridge/raminit_mrc.c
M src/northbridge/intel/sandybridge/romstage.c
M src/soc/amd/picasso/bootblock/pre_c.S
M src/soc/amd/picasso/romstage.c
M src/soc/amd/stoneyridge/chip.c
M src/soc/amd/stoneyridge/romstage.c
M src/soc/intel/broadwell/romstage/romstage.c
M src/soc/intel/common/block/cpu/car/cache_as_ram.S
M src/soc/intel/xeon_sp/romstage.c
22 files changed, 79 insertions(+), 81 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/03/42503/4