[coreboot-gerrit] Change in coreboot[master]: pcengines/apu1: Switch away from ROMCC_BOOTBLOCK

[Patrick Georgi (Code Review)]

Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/37332 )

Change subject: pcengines/apu1: Switch away from ROMCC_BOOTBLOCK
......................................................................

pcengines/apu1: Switch away from ROMCC_BOOTBLOCK

TEST=boot PC Engines apu1 with C bootblock patch and launch
Debian with Linux kernel 4.14.50

Signed-off-by: Michał Żygowski 
Change-Id: I36af6d3871a57f462a7508745663d9759de1c47d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37332
Reviewed-by: Angel Pons 
Reviewed-by: HAOUAS Elyes 
Reviewed-by: Kyösti Mälkki 
Tested-by: build bot (Jenkins) 
---
M src/mainboard/pcengines/apu1/Kconfig
M src/mainboard/pcengines/apu1/Makefile.inc
A src/mainboard/pcengines/apu1/bootblock.c
M src/mainboard/pcengines/apu1/romstage.c
4 files changed, 27 insertions(+), 3 deletions(-)

Approvals:
  build bot (Jenkins): Verified
  Kyösti Mälkki: Looks good to me, approved
  HAOUAS Elyes: Looks good to me, but someone else must approve
  Angel Pons: Looks good to me, approved

diff --git a/src/mainboard/pcengines/apu1/Kconfig b/src/mainboard/pcengines/apu1/Kconfig
index 1684236..3396845 100644
--- a/src/mainboard/pcengines/apu1/Kconfig
+++ b/src/mainboard/pcengines/apu1/Kconfig
@@ -18,7 +18,6 @@

config BOARD_SPECIFIC_OPTIONS
    def_bool y
-	select ROMCC_BOOTBLOCK
    select CPU_AMD_AGESA_FAMILY14
    select NORTHBRIDGE_AMD_AGESA_FAMILY14
    select SOUTHBRIDGE_AMD_CIMX_SB800
diff --git a/src/mainboard/pcengines/apu1/Makefile.inc b/src/mainboard/pcengines/apu1/Makefile.inc
index 543ac97..3aa3bbe 100644
--- a/src/mainboard/pcengines/apu1/Makefile.inc
+++ b/src/mainboard/pcengines/apu1/Makefile.inc
@@ -21,6 +21,8 @@
 pci$(stripped_ahcibios_id).rom-type := optionrom
 endif

+bootblock-y += bootblock.c
+
 romstage-y += buildOpts.c
 romstage-y += BiosCallOuts.c
 romstage-y += OemCustomize.c
diff --git a/src/mainboard/pcengines/apu1/bootblock.c b/src/mainboard/pcengines/apu1/bootblock.c
new file mode 100644
index 0000000..2d34cba
--- /dev/null
+++ b/src/mainboard/pcengines/apu1/bootblock.c
@@ -0,0 +1,25 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include <bootblock_common.h>
+#include <device/pnp_type.h>
+#include <superio/nuvoton/common/nuvoton.h>
+#include <superio/nuvoton/nct5104d/nct5104d.h>
+
+#define SIO_PORT 0x2e
+#define SERIAL_DEV PNP_DEV(SIO_PORT, NCT5104D_SP1)
+
+void bootblock_mainboard_early_init(void)
+{
+	nuvoton_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
+}
diff --git a/src/mainboard/pcengines/apu1/romstage.c b/src/mainboard/pcengines/apu1/romstage.c
index da0e0d3..20a6318 100644
--- a/src/mainboard/pcengines/apu1/romstage.c
+++ b/src/mainboard/pcengines/apu1/romstage.c
@@ -61,7 +61,5 @@

void board_BeforeAgesa(struct sysinfo *cb)
 {
-	sb_Poweron_Init();
    early_lpc_init();
-	nuvoton_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
 }