Marshall Dawson has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/48488 )
Change subject: soc/amd/cezanne: add 0xcf9 reset ......................................................................
Patch Set 3:
(1 comment)
https://review.coreboot.org/c/coreboot/+/48488/3/src/soc/amd/cezanne/reset.c File src/soc/amd/cezanne/reset.c:
https://review.coreboot.org/c/coreboot/+/48488/3/src/soc/amd/cezanne/reset.c... PS3, Line 49: void chipset_handle_reset(uint32_t status) Hmm, how did this build correctly? This is prototyped in src/drivers/intel/fsp2_0/include/fsp/util.h. Did one of our other header files include it for us?
Could consider adding this function later. Also, beyond the scope of this patch, this function could be commonized, similar to soc/intel/common/fsp_reset.
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