Christian Gmeiner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/32327 )
Change subject: payload/seabios: Fix CBFS location on APL platform ......................................................................
Patch Set 3:
(1 comment)
https://review.coreboot.org/#/c/32327/3/payloads/external/SeaBIOS/Makefile File payloads/external/SeaBIOS/Makefile:
https://review.coreboot.org/#/c/32327/3/payloads/external/SeaBIOS/Makefile@4... PS3, Line 43: echo "CONFIG_CBFS_LOCATION=0xfffc0000" >> seabios/.config
Or would it make sense to have a look at the Intel descriptor to get the location and length of the […]
The descriptor (IFD) is not mapped into RAM :/ The first non 0xff content I see here starts at 0xff102000 and is the IFWI. This confirms what is documented in mmap_boot.c
/* * BIOS region on the flash is mapped right below 4GiB in the address * space. However, 256KiB right below 4GiB is decoded by read-only SRAM and not * boot media. * * +-----------+ 0 * | | * | | * | | * | | * | | * | | * | | * | | * +--------+ | | * | IFD | | | * bios_start +---> +--------+------------------> +-----------+ 4GiB - bios_size * ^ | | ^ | | * | | | | | | * | | | bios_mapped_size | BIOS | * | | BIOS | | | | * bios_size | | | | | * | | | v | | * | | +------------------> +-----------+ 4GiB - 256KiB * | | | | Read only | * v | | | SRAM | * bios_end +---> +--------+ +-----------+ 4GiB * | Device | * | ext | * +--------+ * */