Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/44355 )
Change subject: soc/intel/tigerlake: Allow fine grained control of S0iX states ......................................................................
Patch Set 2: Code-Review+2
(3 comments)
https://review.coreboot.org/c/coreboot/+/44355/2//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/44355/2//COMMIT_MSG@12 PS2, Line 12: BUG=?
https://review.coreboot.org/c/coreboot/+/44355/2/src/soc/intel/tigerlake/chi... File src/soc/intel/tigerlake/chip.h:
https://review.coreboot.org/c/coreboot/+/44355/2/src/soc/intel/tigerlake/chi... PS2, Line 94: uint8_t enum lpm_state_mask
https://review.coreboot.org/c/coreboot/+/44355/2/src/soc/intel/tigerlake/fsp... File src/soc/intel/tigerlake/fsp_params.c:
https://review.coreboot.org/c/coreboot/+/44355/2/src/soc/intel/tigerlake/fsp... PS2, Line 212: params->LpmStateEnableMask = config->LpmStateEnableMask; Just a note: This change should land with the mainboard change as a single unit. Else, S0ix will be broken for volteer.