[coreboot-gerrit] Change in coreboot[master]: mb/google/dedede: Add EMMC configuration

[Karthik Ramasubramanian (Code Review)]

Karthik Ramasubramanian has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/38856 )

Change subject: mb/google/dedede: Add EMMC configuration
......................................................................

mb/google/dedede: Add EMMC configuration

Turn on EMMC device and leave the HS400 mode disabled. Configure the
GPIOs associated with EMMC.

BUG=None
TEST=Build the mainboard.

Signed-off-by: Karthikeyan Ramasubramanian 
Change-Id: Ic27c68f4622eec5b2930dc38186b82d895d3f67c
---
M src/mainboard/google/dedede/variants/baseboard/devicetree.cb
M src/mainboard/google/dedede/variants/baseboard/gpio.c
2 files changed, 29 insertions(+), 1 deletion(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/56/38856/1

diff --git a/src/mainboard/google/dedede/variants/baseboard/devicetree.cb b/src/mainboard/google/dedede/variants/baseboard/devicetree.cb
index 9dfd6b7..95205cd 100644
--- a/src/mainboard/google/dedede/variants/baseboard/devicetree.cb
+++ b/src/mainboard/google/dedede/variants/baseboard/devicetree.cb
@@ -69,6 +69,9 @@
    	[PchSerialIoIndexUART2] = PchSerialIoSkipInit,
    }"

+	# Disable EMMC HS400 mode
+	register "ScsEmmcHs400Enabled" = "0"
+
    # Intel Common SoC Config
    #+-------------------+---------------------------+
    #| Field             |  Value                    |
@@ -129,7 +132,7 @@
    	device pci 19.0 on  end # I2C 4
    	device pci 19.1 off end # I2C 5
    	device pci 19.2 on  end # UART 2
-		device pci 1a.0 off end # eMMC
+		device pci 1a.0 on  end # eMMC
    	device pci 1c.0 off end # PCI Express Root Port 1
    	device pci 1c.1 off end # PCI Express Root Port 2
    	device pci 1c.2 off end # PCI Express Root Port 3
diff --git a/src/mainboard/google/dedede/variants/baseboard/gpio.c b/src/mainboard/google/dedede/variants/baseboard/gpio.c
index 9ee4dfc..e69dd27 100644
--- a/src/mainboard/google/dedede/variants/baseboard/gpio.c
+++ b/src/mainboard/google/dedede/variants/baseboard/gpio.c
@@ -58,6 +58,31 @@
    /* C23 : UART2_CTS_N */
    PAD_NC(GPP_C23, DN_20K),

+	/* F7  : EMMC_CMD */
+	PAD_CFG_NF(GPP_F7, NONE, DEEP, NF1),
+	/* F8  : EMMC_DATA0 */
+	PAD_CFG_NF(GPP_F8, NONE, DEEP, NF1),
+	/* F9  : EMMC_DATA1 */
+	PAD_CFG_NF(GPP_F9, NONE, DEEP, NF1),
+	/* F10 : EMMC_DATA2 */
+	PAD_CFG_NF(GPP_F10, NONE, DEEP, NF1),
+	/* F11 : EMMC_DATA3 */
+	PAD_CFG_NF(GPP_F11, NONE, DEEP, NF1),
+	/* F12 : EMMC_DATA4 */
+	PAD_CFG_NF(GPP_F12, NONE, DEEP, NF1),
+	/* F13 : EMMC_DATA5 */
+	PAD_CFG_NF(GPP_F13, NONE, DEEP, NF1),
+	/* F14 : EMMC_DATA6 */
+	PAD_CFG_NF(GPP_F14, NONE, DEEP, NF1),
+	/* F15 : EMMC_DATA7 */
+	PAD_CFG_NF(GPP_F15, NONE, DEEP, NF1),
+	/* F16 : EMMC_RCLK */
+	PAD_CFG_NF(GPP_F16, NONE, DEEP, NF1),
+	/* F17 : EMMC_CLK */
+	PAD_CFG_NF(GPP_F17, NONE, DEEP, NF1),
+	/* F18 : EMMC_RESET_N */
+	PAD_CFG_NF(GPP_F18, NONE, DEEP, NF1),
+
    /* H4  : AP_I2C_TS_SDA */
    PAD_CFG_NF(GPP_H4, NONE, DEEP, NF1),
    /* H5  : AP_I2C_TS_SCL */