[coreboot-gerrit] Change in coreboot[master]: mb/google/brya: Initiate peripheral buses

[EricR Lai (Code Review)]

EricR Lai has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/48295 )

Change subject: mb/google/brya: Initiate peripheral buses
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Patch Set 2:
> Patch Set 2:
> > Patch Set 2:
> > > Patch Set 2:
> > > > Patch Set 2:
> > > >
> > > > @Subrata, I found fspUpd has PcieClkSrcUsage[18],
> > >
> > > Its for unified FSP between ADL-S and P, thats the reason might be but you don't need more than 7 i believe
> > > > and schematic has 0-9B. Is 9B map to PcieClkSrcUsage[10]?
> > >
> > > what is 9B ?
> >
> > GPP_A12/SATAXPCIE1/SATAGP1/SRCCLKREQ9B#
>
> looks like you have CLK REQ 9 so, PcieClkSrcUsage[9] but need to verify ur CLKSRC.

GPP_E0/SATAXPCIE0/SATAGP0/SRCCLKREQ9# This is confused because the pin is different.. Not quite understand it. Both map the same ClkSrc?