[coreboot-gerrit] Change in coreboot[master]: soc/intel/tigerlake: Update fsp params for Jasper Lake

[Karthik Ramasubramanian (Code Review)]

Karthik Ramasubramanian has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38461 )

Change subject: soc/intel/tigerlake: Update fsp params for Jasper Lake
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Patch Set 16:

(1 comment)

https://review.coreboot.org/c/coreboot/+/38461/16/src/soc/intel/tigerlake/ch... 
File src/soc/intel/tigerlake/chip.h:

https://review.coreboot.org/c/coreboot/+/38461/16/src/soc/intel/tigerlake/ch... 
PS16, Line 208: 	enum {
              : 		DEBUG_INTERFACE_RAM  = 0x1,
              : 		DEBUG_INTERFACE_UART = 0x2,
              : 		DEBUG_INTERFACE_USB3 = 0x4,
              : 		DEBUG_INTERFACE_SERIAL_IO  = 0x8,
              : 		DEBUG_INTERFACE_TRACEHUB = 0x10
              : 	} debug_interface_flag;
As per the FSP UPD, Bit 2 is not used. But here it is used. Please find the below comment in the Fspmupd.h

Debug Interfaces. BIT0-RAM, BIT1-UART, BIT3-USB3, BIT4-Serial IO, BIT5-TraceHub,
BIT2 - Not used.