[coreboot-gerrit] Change in coreboot[master]: soc/intel/tigerlake: Correct FSP log interface

[Aamir Bohra (Code Review)]

Aamir Bohra has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39280 )

Change subject: soc/intel/tigerlake: Correct FSP log interface
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Patch Set 15:

(1 comment)

https://review.coreboot.org/c/coreboot/+/39280/15/src/soc/intel/tigerlake/ro... 
File src/soc/intel/tigerlake/romstage/fsp_params_jsl.c:

https://review.coreboot.org/c/coreboot/+/39280/15/src/soc/intel/tigerlake/ro... 
PS15, Line 29: const struct device *tracehub = pcidev_path_on_root(PCH_DEVFN_TRACEHUB);
you can use the dev variable:

dev = pcidev_path_on_root(PCH_DEVFN_TRACEHUB);
if (dev && dev->enabled && config->TraceHubMode) {
    	m_cfg->PcdDebugInterfaceFlags |= DEBUG_INTERFACE_TRACEHUB;
    	m_cfg->PchTraceHubMode = config->TraceHubMode;
    	m_cfg->CpuTraceHubMode = config->TraceHubMode;
}