Attention is currently required from: Andrey Petrov, Patrick Rudolph. Kyösti Mälkki has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/49820 )
Change subject: ELOG: Add const qualifier for chipset_power_state ......................................................................
ELOG: Add const qualifier for chipset_power_state
It is never allowed for ELOG to modify the state.
Change-Id: Ie24df3969a3744f27b23997471666e2490e24b84 Signed-off-by: Kyösti Mälkki kyosti.malkki@gmail.com --- M src/soc/intel/alderlake/elog.c M src/soc/intel/apollolake/elog.c M src/soc/intel/broadwell/pch/elog.c M src/soc/intel/cannonlake/elog.c M src/soc/intel/elkhartlake/elog.c M src/soc/intel/icelake/elog.c M src/soc/intel/jasperlake/elog.c M src/soc/intel/skylake/elog.c M src/soc/intel/tigerlake/elog.c 9 files changed, 18 insertions(+), 18 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/20/49820/1
diff --git a/src/soc/intel/alderlake/elog.c b/src/soc/intel/alderlake/elog.c index 84f0a7e..8ec1107 100644 --- a/src/soc/intel/alderlake/elog.c +++ b/src/soc/intel/alderlake/elog.c @@ -20,7 +20,7 @@ } }
-static void pch_log_wake_source(struct chipset_power_state *ps) +static void pch_log_wake_source(const struct chipset_power_state *ps) { /* Power Button */ if (ps->pm1_sts & PWRBTN_STS) @@ -54,7 +54,7 @@ pch_log_gpio_gpe(ps->gpe0_sts[GPE_STD], ps->gpe0_en[GPE_STD], 96); }
-static void pch_log_power_and_resets(struct chipset_power_state *ps) +static void pch_log_power_and_resets(const struct chipset_power_state *ps) { /* Thermal Trip */ if (ps->gblrst_cause[0] & GBLRST_CAUSE0_THERMTRIP) diff --git a/src/soc/intel/apollolake/elog.c b/src/soc/intel/apollolake/elog.c index b65ab10..d17d407 100644 --- a/src/soc/intel/apollolake/elog.c +++ b/src/soc/intel/apollolake/elog.c @@ -23,7 +23,7 @@ } }
-static void pch_log_wake_source(struct chipset_power_state *ps) +static void pch_log_wake_source(const struct chipset_power_state *ps) { const struct xhci_wake_info xhci_wake_info[] = { { PCH_DEVFN_XHCI, ELOG_WAKE_SOURCE_PME_XHCI }, @@ -65,7 +65,7 @@ pch_log_gpio_gpe(ps->gpe0_sts[GPE0_D], ps->gpe0_en[GPE0_D], 96); }
-static void pch_log_power_and_resets(struct chipset_power_state *ps) +static void pch_log_power_and_resets(const struct chipset_power_state *ps) { /* RTC Reset */ if (ps->gen_pmcon1 & RPS) diff --git a/src/soc/intel/broadwell/pch/elog.c b/src/soc/intel/broadwell/pch/elog.c index 9271e27..1d4d773 100644 --- a/src/soc/intel/broadwell/pch/elog.c +++ b/src/soc/intel/broadwell/pch/elog.c @@ -20,7 +20,7 @@ } }
-static void pch_log_wake_source(struct chipset_power_state *ps) +static void pch_log_wake_source(const struct chipset_power_state *ps) { /* Power Button */ if (ps->pm1_sts & PWRBTN_STS) @@ -56,7 +56,7 @@ pch_log_gpio_gpe(ps->gpe0_sts[GPE_94_64], ps->gpe0_en[GPE_94_64], 64); }
-static void pch_log_power_and_resets(struct chipset_power_state *ps) +static void pch_log_power_and_resets(const struct chipset_power_state *ps) { /* Thermal Trip Status */ if (ps->gen_pmcon2 & THERMTRIP_STS) diff --git a/src/soc/intel/cannonlake/elog.c b/src/soc/intel/cannonlake/elog.c index 104a78c..4c39988 100644 --- a/src/soc/intel/cannonlake/elog.c +++ b/src/soc/intel/cannonlake/elog.c @@ -91,7 +91,7 @@ } }
-static void pch_log_wake_source(struct chipset_power_state *ps) +static void pch_log_wake_source(const struct chipset_power_state *ps) { /* Power Button */ if (ps->pm1_sts & PWRBTN_STS) @@ -125,7 +125,7 @@ pch_log_gpio_gpe(ps->gpe0_sts[GPE_STD], ps->gpe0_en[GPE_STD], 96); }
-static void pch_log_power_and_resets(struct chipset_power_state *ps) +static void pch_log_power_and_resets(const struct chipset_power_state *ps) { /* Thermal Trip */ if (ps->gblrst_cause[0] & GBLRST_CAUSE0_THERMTRIP) diff --git a/src/soc/intel/elkhartlake/elog.c b/src/soc/intel/elkhartlake/elog.c index c88efc8..14e463c 100644 --- a/src/soc/intel/elkhartlake/elog.c +++ b/src/soc/intel/elkhartlake/elog.c @@ -20,7 +20,7 @@ } }
-static void pch_log_wake_source(struct chipset_power_state *ps) +static void pch_log_wake_source(const struct chipset_power_state *ps) { /* Power Button */ if (ps->pm1_sts & PWRBTN_STS) @@ -54,7 +54,7 @@ pch_log_gpio_gpe(ps->gpe0_sts[GPE_STD], ps->gpe0_en[GPE_STD], 96); }
-static void pch_log_power_and_resets(struct chipset_power_state *ps) +static void pch_log_power_and_resets(const struct chipset_power_state *ps) { /* Thermal Trip */ if (ps->gblrst_cause[0] & GBLRST_CAUSE0_THERMTRIP) diff --git a/src/soc/intel/icelake/elog.c b/src/soc/intel/icelake/elog.c index 235dc6e..4967fde 100644 --- a/src/soc/intel/icelake/elog.c +++ b/src/soc/intel/icelake/elog.c @@ -20,7 +20,7 @@ } }
-static void pch_log_wake_source(struct chipset_power_state *ps) +static void pch_log_wake_source(const struct chipset_power_state *ps) { /* Power Button */ if (ps->pm1_sts & PWRBTN_STS) @@ -54,7 +54,7 @@ pch_log_gpio_gpe(ps->gpe0_sts[GPE_STD], ps->gpe0_en[GPE_STD], 96); }
-static void pch_log_power_and_resets(struct chipset_power_state *ps) +static void pch_log_power_and_resets(const struct chipset_power_state *ps) { /* Thermal Trip */ if (ps->gblrst_cause[0] & GBLRST_CAUSE0_THERMTRIP) diff --git a/src/soc/intel/jasperlake/elog.c b/src/soc/intel/jasperlake/elog.c index cb9625a..ccf6fd0 100644 --- a/src/soc/intel/jasperlake/elog.c +++ b/src/soc/intel/jasperlake/elog.c @@ -100,7 +100,7 @@ elog_add_event_wake(ELOG_WAKE_SOURCE_PME_INTERNAL, 0); }
-static void pch_log_wake_source(struct chipset_power_state *ps) +static void pch_log_wake_source(const struct chipset_power_state *ps) { /* Power Button */ if (ps->pm1_sts & PWRBTN_STS) @@ -134,7 +134,7 @@ pch_log_gpio_gpe(ps->gpe0_sts[GPE_STD], ps->gpe0_en[GPE_STD], 96); }
-static void pch_log_power_and_resets(struct chipset_power_state *ps) +static void pch_log_power_and_resets(const struct chipset_power_state *ps) { /* Thermal Trip */ if (ps->gblrst_cause[0] & GBLRST_CAUSE0_THERMTRIP) diff --git a/src/soc/intel/skylake/elog.c b/src/soc/intel/skylake/elog.c index 1332e2d..c9b719f 100644 --- a/src/soc/intel/skylake/elog.c +++ b/src/soc/intel/skylake/elog.c @@ -131,7 +131,7 @@ } }
-static void pch_log_wake_source(struct chipset_power_state *ps) +static void pch_log_wake_source(const struct chipset_power_state *ps) { /* Power Button */ if (ps->pm1_sts & PWRBTN_STS) @@ -173,7 +173,7 @@ pch_log_gpio_gpe(ps->gpe0_sts[GPE_STD], ps->gpe0_en[GPE_STD], 96); }
-static void pch_log_power_and_resets(struct chipset_power_state *ps) +static void pch_log_power_and_resets(const struct chipset_power_state *ps) { bool deep_sx;
diff --git a/src/soc/intel/tigerlake/elog.c b/src/soc/intel/tigerlake/elog.c index 7f40a37..878959a 100644 --- a/src/soc/intel/tigerlake/elog.c +++ b/src/soc/intel/tigerlake/elog.c @@ -126,7 +126,7 @@ elog_add_event_wake(ELOG_WAKE_SOURCE_PME_INTERNAL, 0); }
-static void pch_log_wake_source(struct chipset_power_state *ps) +static void pch_log_wake_source(const struct chipset_power_state *ps) { /* Power Button */ if (ps->pm1_sts & PWRBTN_STS) @@ -160,7 +160,7 @@ pch_log_gpio_gpe(ps->gpe0_sts[GPE_STD], ps->gpe0_en[GPE_STD], 96); }
-static void pch_log_power_and_resets(struct chipset_power_state *ps) +static void pch_log_power_and_resets(const struct chipset_power_state *ps) { /* Thermal Trip */ if (ps->gblrst_cause[0] & GBLRST_CAUSE0_THERMTRIP)