[coreboot-gerrit] Change in coreboot[master]: arch/x86: Simplified postcar WB MTRR setup

[Subrata Banik (Code Review)]

Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/34897 )

Change subject: arch/x86: Simplified postcar WB MTRR setup
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Patch Set 1:
> Patch Set 1:
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> Would this approach, if applied to all intel platforms, have some issues? Do we need UC holes between cbmem_top() and TSEG?

kindly take a look and read this entire topic https://review.coreboot.org/q/topic:%22dram_cache_wb%22+(status:open%20OR%20...) why we have dropped WB and moved to WP for intermediate caching (cbmem_top -16MB) to cbmem-top