Aaron Durbin has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/30985 )
Change subject: postcarpayload: Boot to payload from postcar stage directly [WIP] ......................................................................
Patch Set 20:
(5 comments)
This change is ready for review.
https://review.coreboot.org/#/c/30985/20/src/arch/x86/c_postcar_start.S File src/arch/x86/c_postcar_start.S:
https://review.coreboot.org/#/c/30985/20/src/arch/x86/c_postcar_start.S@12 PS20, Line 12: */ Why is this needed? And why are we effectively duplicating things from ramstage?
https://review.coreboot.org/#/c/30985/20/src/include/rules_lite.h File src/include/rules_lite.h:
https://review.coreboot.org/#/c/30985/20/src/include/rules_lite.h@32 PS20, Line 32: */ The need of this file seems like a big hack.
https://review.coreboot.org/#/c/30985/20/src/mainboard/google/dragonegg/dsdt... File src/mainboard/google/dragonegg/dsdt.asl:
https://review.coreboot.org/#/c/30985/20/src/mainboard/google/dragonegg/dsdt... PS20, Line 63: Scope (_SB.PCI0.SPI0) Why is this change in this CL?
https://review.coreboot.org/#/c/30985/20/src/soc/intel/common/block/include/... File src/soc/intel/common/block/include/intelblocks/pcie.h:
https://review.coreboot.org/#/c/30985/20/src/soc/intel/common/block/include/... PS20, Line 22: void pcie_set_L1_ss_max_latency(struct device *dev, unsigned int offset); Why is this here?
https://review.coreboot.org/#/c/30985/20/src/soc/intel/icelake/payload_init.... File src/soc/intel/icelake/payload_init.c:
https://review.coreboot.org/#/c/30985/20/src/soc/intel/icelake/payload_init.... PS20, Line 71: #define IGD_BAR_SIZE_2 0x10000000 So we're statically allocating resources? This is not a scalable approach. And doesn't the existence of this file indicate this approach is just trying to hack something in?