This change is ready for review.
5 comments:
File src/arch/x86/c_postcar_start.S:
Why is this needed? And why are we effectively duplicating things from ramstage?
File src/include/rules_lite.h:
The need of this file seems like a big hack.
File src/mainboard/google/dragonegg/dsdt.asl:
Patch Set #20, Line 63: Scope (\_SB.PCI0.SPI0)
Why is this change in this CL?
File src/soc/intel/common/block/include/intelblocks/pcie.h:
Patch Set #20, Line 22: void pcie_set_L1_ss_max_latency(struct device *dev, unsigned int offset);
Why is this here?
File src/soc/intel/icelake/payload_init.c:
Patch Set #20, Line 71: #define IGD_BAR_SIZE_2 0x10000000
So we're statically allocating resources? This is not a scalable approach. And doesn't the existence of this file indicate this approach is just trying to hack something in?
To view, visit change 30985. To unsubscribe, or for help writing mail filters, visit settings.