[coreboot-gerrit] Change in coreboot[master]: mb/siemens/mc_apl6: Adjust clock lines used on PCIe-2-PCI bridge

[Werner Zeh (Code Review)]

Werner Zeh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/36671 )

Change subject: mb/siemens/mc_apl6: Adjust clock lines used on PCIe-2-PCI bridge
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Patch Set 1:

(1 comment)

https://review.coreboot.org/c/coreboot/+/36671/1/src/mainboard/siemens/mc_ap... 
File src/mainboard/siemens/mc_apl1/variants/mc_apl6/mainboard.c:

https://review.coreboot.org/c/coreboot/+/36671/1/src/mainboard/siemens/mc_ap... 
PS1, Line 68: 			pci_write_config8(parent, 0xd8, 0x70);
> if only output 4 is enabled, should the value not be 0x0F?

Yes, you are right. Got the wrong register meaning.
Will adjust.