[coreboot-gerrit] Change in coreboot[master]: soc/intel/ehl: Replace dt `HeciEnabled` by `CSE disable` config

[Subrata Banik (Code Review)]

Attention is currently required from: Patrick Rudolph.
Hello Patrick Rudolph,

I'd like you to reexamine a change. Please visit

https://review.coreboot.org/c/coreboot/+/60727

to look at the new patch set (#2).

Change subject: soc/intel/ehl: Replace dt `HeciEnabled` by `CSE disable` config
......................................................................

soc/intel/ehl: Replace dt `HeciEnabled` by `CSE disable` config

Lists of changes:

1. Drop `HeciEnabled` from dt and dt chip configuration.
2. Replace all logic that disables CSE based on the `HeciEnabled`
chip config with `DISABLE_CSE_AT_PRE_BOOT` config.

Mainboards that choose to make CSE enable during boot don't select
`cse disable` config.

Signed-off-by: Subrata Banik 
Change-Id: I76c625e6221fdef1343599e7dbc7739caa91bf98
---
M src/mainboard/intel/elkhartlake_crb/variants/ehlcrb/devicetree.cb
M src/mainboard/siemens/mc_ehl/variants/mc_ehl1/devicetree.cb
M src/mainboard/siemens/mc_ehl/variants/mc_ehl2/devicetree.cb
M src/soc/intel/elkhartlake/chip.h
M src/soc/intel/elkhartlake/smihandler.c
5 files changed, 1 insertion(+), 18 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/27/60727/2