Hello Patrick Rudolph,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/32283
to look at the new patch set (#2).
Change subject: soc/intel/../../timer: Calculate TSC frequency based on CPUID 0x15 ......................................................................
soc/intel/../../timer: Calculate TSC frequency based on CPUID 0x15
This patch ensures to follow Intel SDM Vol 3B Sec 18.7.3 to calculate norminal TSC frequency.
As per SDM recommendation: For any processor in which CPUID.15H is enumerated and MSR_PLATFORM_INFO[15:8] (which gives the scalable bus frequency) is available, a more accurate frequency can be obtained by using CPUID.15H
BUG=b:129839774 TEST=Calculate TSC frequency using below methods 1. TSC freq calculated based on MSR 0xCE tsc: Detected 1600.000 MHz processor
2. TSC freq calculated based on CPUID 0x15 tsc: Detected 1612.800 MHz TSC
Method 2 actually reduce ~25mSec of boot performance time.
Change-Id: I9ff4b9159a94e61b7e634bd6095f7cc6d7df87c7 Signed-off-by: Subrata Banik subrata.banik@intel.com --- A src/arch/x86/include/arch/intel-family.h M src/soc/intel/common/block/timer/timer.c 2 files changed, 161 insertions(+), 3 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/83/32283/2