Subrata Banik has submitted this change. ( https://review.coreboot.org/c/coreboot/+/85781?usp=email )
Change subject: soc/intel/pantherlake: Update the Thunderbolt lcap_port_base to 21 ......................................................................
soc/intel/pantherlake: Update the Thunderbolt lcap_port_base to 21
Document #815002 Panther Lake H Processor - 2.3 Device IDs - Table 8 "Other Device ID" specifies that the first Thunderbolt PCIe root port number is 21.
The previous offset of 0x10, inherited from Meteor Lake code, caused an issue that resulted in:
- Temporary deactivation of Thunderbolt PCI devices during ramstage
- Failure to generate critical ACPI SSDT power management data for the port
This error led to instability in PCIe tunneling during power state transitions.
Change-Id: I44f91f954a4ec06c56dcc90d97e7da2193e9acf2 Signed-off-by: Jeremy Compostella jeremy.compostella@intel.com Reviewed-on: https://review.coreboot.org/c/coreboot/+/85781 Reviewed-by: Subrata Banik subratabanik@google.com Tested-by: build bot (Jenkins) no-reply@coreboot.org --- M src/soc/intel/pantherlake/pcie_rp.c 1 file changed, 7 insertions(+), 5 deletions(-)
Approvals: build bot (Jenkins): Verified Subrata Banik: Looks good to me, approved
diff --git a/src/soc/intel/pantherlake/pcie_rp.c b/src/soc/intel/pantherlake/pcie_rp.c index 1b302fd..604e7af 100644 --- a/src/soc/intel/pantherlake/pcie_rp.c +++ b/src/soc/intel/pantherlake/pcie_rp.c @@ -5,13 +5,15 @@ #include <soc/pcie.h>
/* - * TBT's LCAP registers are returning port index which starts from 0x10 (Usually for other PCIe - * root ports index starts from 1). Thus keeping lcap_port_base 0x10 for TBT, so that coreboot's - * PCIe remapping logic can return correct index (0-based) - */ + * Document #815002 Panther Lake H Processor - 2.3 Device IDs - Table 8 "Other Device ID" + * specifies that the first Thunderbolt PCIe root port number is 21. TBT's LCAP registers return + * port index which starts from 21 (usually for other PCIe root ports index starts from + * 1). Thus, keeping lcap_port_base 21 for TBT, so that coreboot's PCIe remapping logic can + * return a correct index (0-based). +*/
static const struct pcie_rp_group tbt_rp_groups[] = { - { .slot = PCI_DEV_SLOT_TBT, .count = CONFIG_MAX_TBT_ROOT_PORTS, .lcap_port_base = 0x10 }, + { .slot = PCI_DEV_SLOT_TBT, .count = CONFIG_MAX_TBT_ROOT_PORTS, .lcap_port_base = 21 }, { 0 } };