[coreboot-gerrit] Change in coreboot[master]: soc/intel/jasperlake: Enable VT-d and generate DMAR Table

[Meera Ravindranath (Code Review)]

Meera Ravindranath has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/47506 )

Change subject: soc/intel/jasperlake: Enable VT-d and generate DMAR Table
......................................................................

soc/intel/jasperlake: Enable VT-d and generate DMAR Table

Update UPDs required for the creation of DMAR table.

TEST=Build Dedede, boot to kernel and check dmesg if DMAR
     table exists.

Signed-off-by: Meera Ravindranath 
Change-Id: I97a9f2df185002a4e58eaa910f867acd0b97ec2b
---
M src/soc/intel/jasperlake/romstage/fsp_params.c
1 file changed, 12 insertions(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/06/47506/1

diff --git a/src/soc/intel/jasperlake/romstage/fsp_params.c b/src/soc/intel/jasperlake/romstage/fsp_params.c
index 528ef0f..d420351 100644
--- a/src/soc/intel/jasperlake/romstage/fsp_params.c
+++ b/src/soc/intel/jasperlake/romstage/fsp_params.c
@@ -4,6 +4,7 @@
 #include <console/console.h>
 #include <device/device.h>
 #include <fsp/util.h>
+#include <soc/iomap.h>
 #include <soc/pci_devs.h>
 #include <soc/romstage.h>
 #include <soc/soc_chip.h>
@@ -81,6 +82,17 @@

/* VT-d config */
    m_cfg->VtdDisable = 0;
+	m_cfg->VtdIopEnable = 0x1;
+
+	if (m_cfg->InternalGfx) {
+		m_cfg->VtdIgdEnable = 0x1;
+		m_cfg->VtdBaseAddress[0] = GFXVT_BASE_ADDRESS;
+	}
+
+	if (m_cfg->SaIpuEnable) {
+		m_cfg->VtdIpuEnable = 0x1;
+		m_cfg->VtdBaseAddress[1] = IPUVT_BASE_ADDRESS;
+	}

m_cfg->SerialIoUartDebugControllerNumber = CONFIG_UART_FOR_CONSOLE;
    m_cfg->SerialIoUartDebugMode = config->SerialIoUartMode[CONFIG_UART_FOR_CONSOLE];