Christian Walter has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/37606 )
Change subject: FIX Supermicro ......................................................................
FIX Supermicro
Change-Id: I5450d133e2ef1cc090a5746c260917394420511a Signed-off-by: Christian Walter christian.walter@9elements.com --- M src/mainboard/supermicro/x11sch/Kconfig M src/mainboard/supermicro/x11sch/variants/x11sch-f/gpio.c M src/mainboard/supermicro/x11sch/variants/x11sch-f/overridetree.cb 3 files changed, 30 insertions(+), 29 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/06/37606/1
diff --git a/src/mainboard/supermicro/x11sch/Kconfig b/src/mainboard/supermicro/x11sch/Kconfig index c658c8a..4c7e6fb 100644 --- a/src/mainboard/supermicro/x11sch/Kconfig +++ b/src/mainboard/supermicro/x11sch/Kconfig @@ -7,8 +7,10 @@ select HAVE_ACPI_TABLES select SOC_INTEL_CANNONLAKE_PCH_H select SUPERIO_ASPEED_COMMON_PRE_RAM + select SUPERIO_ASPEED_AST2400 select DRIVERS_ASPEED_AST_COMMON select DRIVERS_ASPEED_AST2050 + select SOC_INTEL_COMMON_BLOCK_LPC_COMB_ENABLE
config MAINBOARD_FAMILY string diff --git a/src/mainboard/supermicro/x11sch/variants/x11sch-f/gpio.c b/src/mainboard/supermicro/x11sch/variants/x11sch-f/gpio.c index 7ba738a..f30e8b4 100644 --- a/src/mainboard/supermicro/x11sch/variants/x11sch-f/gpio.c +++ b/src/mainboard/supermicro/x11sch/variants/x11sch-f/gpio.c @@ -19,21 +19,21 @@ /* Pad configuration in ramstage */ static const struct pad_config gpio_table[] = {
- /* ESPI_ALERT1# */ _PAD_CFG_STRUCT(GPP_A0, 0x44000f02, 0x00000000), -/* ESPI_IO0 */ _PAD_CFG_STRUCT(GPP_A1, 0x44000f00, 0x00000000), -/* ESPI_IO1 */ _PAD_CFG_STRUCT(GPP_A2, 0x44000f02, 0x00000000), -/* ESPI_IO2 */ _PAD_CFG_STRUCT(GPP_A3, 0x44000f00, 0x00000000), -/* ESPI_IO3 */ _PAD_CFG_STRUCT(GPP_A4, 0x44000f00, 0x00000000), -/* ESPI_CS0# */ _PAD_CFG_STRUCT(GPP_A5, 0x44000f00, 0x00000000), + /* ESPI_ALERT1# */ //_PAD_CFG_STRUCT(GPP_A0, 0x44000f02, 0x00000000), +/* ESPI_IO0 */ //_PAD_CFG_STRUCT(GPP_A1, 0x44000f00, 0x00000000), +/* ESPI_IO1 */ //_PAD_CFG_STRUCT(GPP_A2, 0x44000f02, 0x00000000), +/* ESPI_IO2 */ //_PAD_CFG_STRUCT(GPP_A3, 0x44000f00, 0x00000000), +/* ESPI_IO3 */ //_PAD_CFG_STRUCT(GPP_A4, 0x44000f00, 0x00000000), +/* ESPI_CS0# */ //_PAD_CFG_STRUCT(GPP_A5, 0x44000f00, 0x00000000), /* GPIO */ _PAD_CFG_STRUCT(GPP_A6, 0x44000102, 0x00000000), -/* ESPI_ALERT0# */ _PAD_CFG_STRUCT(GPP_A7, 0x44000f02, 0x00000000), +/* ESPI_ALERT0# */ //_PAD_CFG_STRUCT(GPP_A7, 0x44000f02, 0x00000000), /* CLKRUN# */ _PAD_CFG_STRUCT(GPP_A8, 0x44000502, 0x00000000), -/* ESPI_CLK */ _PAD_CFG_STRUCT(GPP_A9, 0x44000f00, 0x00000000), +/* ESPI_CLK */ //_PAD_CFG_STRUCT(GPP_A9, 0x44000f00, 0x00000000), /* CLKOUT_LPC1 */ _PAD_CFG_STRUCT(GPP_A10, 0x44000600, 0x00000000), /* GPIO */ _PAD_CFG_STRUCT(GPP_A11, 0x44000102, 0x00000000), /* GPIO */ _PAD_CFG_STRUCT(GPP_A12, 0x80880102, 0x00000000), /* SUSWARN# */ _PAD_CFG_STRUCT(GPP_A13, 0x44000600, 0x00000000), -/* ESPI_RESET# */ _PAD_CFG_STRUCT(GPP_A14, 0x44000f00, 0x00000000), +/* ESPI_RESET# */ //_PAD_CFG_STRUCT(GPP_A14, 0x44000f00, 0x00000000), /* SUSACK# */ _PAD_CFG_STRUCT(GPP_A15, 0x44000700, 0x00000000), /* GPIO */ _PAD_CFG_STRUCT(GPP_A16, 0x44000200, 0x00000000), /* GPIO */ _PAD_CFG_STRUCT(GPP_A17, 0x44000200, 0x00000000), diff --git a/src/mainboard/supermicro/x11sch/variants/x11sch-f/overridetree.cb b/src/mainboard/supermicro/x11sch/variants/x11sch-f/overridetree.cb index 7e0197c..3904b30 100644 --- a/src/mainboard/supermicro/x11sch/variants/x11sch-f/overridetree.cb +++ b/src/mainboard/supermicro/x11sch/variants/x11sch-f/overridetree.cb @@ -18,7 +18,7 @@ register "SataPortsEnable[6]" = "1" register "SataPortsEnable[7]" = "1"
- register "PchHdaDspEnable" = "0" + register "PchHdaDspEnable" = "1" register "PchHdaAudioLinkHda" = "1"
register "PcieRpEnable[1]" = "1" @@ -97,10 +97,11 @@ register "speed_shift_enable" = "1"
# HECI - register "HeciEnabled" = "1" + register "Heci1Disabled" = "0" + register "Heci3Enabled" = "1"
# Internal GFX - register "InternalGfx" = "0" + register "InternalGfx" = "1"
# Enable S0ix register "s0ix_enable" = "1" @@ -117,40 +118,37 @@ device pci 14.0 on end # USB xHCI device pci 14.1 off end # USB xDCI (OTG) device pci 14.2 on end - device pci 14.5 on end # SDCard device pci 15.0 on end # I2C #0 device pci 15.1 on end # I2C #1 device pci 15.2 off end # I2C #2 device pci 15.3 off end # I2C #3 - device pci 16.0 on end # Management Engine Interface 1 - device pci 16.1 on end # Management Engine Interface 2 - device pci 16.2 off end # Management Engine IDE-R - device pci 16.3 off end # Management Engine KT Redirection - device pci 16.4 on end # Management Engine Interface 3 - device pci 16.5 off end # Management Engine Interface 4 + device pci 16.0 on end # Management Engine Interface + device pci 16.1 on end # Management Engine Interface + device pci 16.4 on end # Management Engine Interface device pci 17.0 on end # SATA - device pci 19.0 off end # I2C #4 device pci 19.2 on end # UART #2 - device pci 1a.0 on end # eMMC - device pci 1b.0 on end - device pci 1b.4 on end # Ethernet - device pci 1b.5 on end # Ethernet - device pci 1c.0 on end # LPC Interface - device pci 1c.1 on end # Aspeed Graphics - device pci 1c.4 on end # NVMe PCIE x4 - device pci 1d.0 on end # PCIE x4 + device pci 1a.0 on end # eMMC + device pci 1b.0 on end + device pci 1b.4 on end # onboard Ethernet + device pci 1b.5 on end # onboard Ethernet + device pci 1c.0 on end # LPC Interface + device pci 1c.1 on end # Aspeed Graphics + device pci 1c.4 on end # NVMe PCIE x4 + device pci 1d.0 on end # PCIE x4 device pci 1e.0 on end # UART #0 - device pci 1f.0 on end # LPC Interface + device pci 1f.0 on # LPC Interface chip superio/common device pnp 4e.0 on chip superio/aspeed/ast2400 device pnp 4e.2 on # SUART1 io 0x60 = 0x3f8 irq 0x70 = 4 + irq 0x71 = 0 end device pnp 4e.3 on # SUART2 io 0x60 = 0x2f8 irq 0x70 = 3 + irq 0x71 = 0 end device pnp 4e.4 off end # SWC device pnp 4e.5 off end # KBC @@ -162,6 +160,7 @@ end end end + end device pci 1f.4 on end # SMBus device pci 1f.5 on end # PCH SPI end