[coreboot-gerrit] [S] Change in coreboot[master]: mb/google/brya: configure GPP_D1 using PAD_CFG_OD_GPO

[Nick Vaccaro (Code Review)]

Attention is currently required from: Tarun Tuli.

Nick Vaccaro has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/74842 )

Change subject: mb/google/brya: configure GPP_D1 using PAD_CFG_OD_GPO
......................................................................

mb/google/brya: configure GPP_D1 using PAD_CFG_OD_GPO

Use the new PAD_CFG_OD_GPO() macro to configure the GPP_D1 gpio for
the open-drain FP_RST_ODL signal.

BUG=b:278732600
BRANCH=firmware-brya-14505.B
TEST='emerge-brya coreboot chromeos-bootimage', flash and boot skolas to
kernel, sleep and wake device and use fingerprint for wake
authentication.

Change-Id: I66ff974c6222e38a7584a756dba0e4714d1e5797
Signed-off-by: Nick Vaccaro 
---
M src/mainboard/google/brya/variants/baseboard/brya/gpio.c
M src/mainboard/google/brya/variants/brya0/gpio.c
M src/mainboard/google/brya/variants/brya0/variant.c
3 files changed, 36 insertions(+), 7 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/42/74842/1

diff --git a/src/mainboard/google/brya/variants/baseboard/brya/gpio.c b/src/mainboard/google/brya/variants/baseboard/brya/gpio.c
index f3ab850..b73384e 100644
--- a/src/mainboard/google/brya/variants/baseboard/brya/gpio.c
+++ b/src/mainboard/google/brya/variants/baseboard/brya/gpio.c
@@ -120,7 +120,7 @@
    /* D0  : ISH_GP0 ==> PCH_FP_BOOT0 */
    PAD_CFG_GPO_LOCK(GPP_D0, 0, LOCK_CONFIG),
    /* D1  : ISH_GP1 ==> FP_RST_ODL */
-	PAD_CFG_GPO_LOCK(GPP_D1, 0, LOCK_CONFIG),
+	PAD_CFG_OD_GPO_LOCK(GPP_D1, LOCK_CONFIG),
    /* D2  : ISH_GP2 ==> EN_FP_PWR */
    PAD_CFG_GPO_LOCK(GPP_D2, 0, LOCK_CONFIG),
    /* D3  : ISH_GP3 ==> WCAM_RST_L */
@@ -402,7 +402,7 @@
     * later on in ramstage. Since reset signal is asserted in bootblock, it results in
     * FPMCU not working after a S3 resume. This is a known issue.
     */
-	PAD_CFG_GPO(GPP_D1, 0, DEEP),
+	PAD_CFG_OD_GPO(GPP_D1, DEEP),
    /* D2  : ISH_GP2 ==> EN_FP_PWR */
    PAD_CFG_GPO(GPP_D2, 1, DEEP),
    /* E13 : THC0_SPI1_IO2 ==> MEM_CH_SEL */
diff --git a/src/mainboard/google/brya/variants/brya0/gpio.c b/src/mainboard/google/brya/variants/brya0/gpio.c
index f406f4b..55d7b26 100644
--- a/src/mainboard/google/brya/variants/brya0/gpio.c
+++ b/src/mainboard/google/brya/variants/brya0/gpio.c
@@ -49,7 +49,7 @@
     * later on in ramstage. Since reset signal is asserted in bootblock, it results in
     * FPMCU not working after a S3 resume. This is a known issue.
     */
-	PAD_CFG_GPO(GPP_D1, 0, DEEP),
+	PAD_CFG_OD_GPO(GPP_D1, DEEP),
    /* D2  : ISH_GP2 ==> EN_FP_PWR */
    PAD_CFG_GPO(GPP_D2, 1, DEEP),
    /* E0  : SATAXPCIE0 ==> WWAN_PERST_L (updated in ramstage) */
@@ -92,7 +92,7 @@
     * later on in ramstage. Since reset signal is asserted in bootblock, it results in
     * FPMCU not working after a S3 resume. This is a known issue.
     */
-	PAD_CFG_GPO(GPP_D1, 0, DEEP),
+	PAD_CFG_OD_GPO(GPP_D1, DEEP),
    /* D2  : ISH_GP2 ==> EN_FP_PWR */
    PAD_CFG_GPO(GPP_D2, 1, DEEP),
    /* D11 : ISH_SPI_MISO ==> EN_PP3300_SSD */
@@ -138,7 +138,7 @@
     * Since reset signal is asserted in bootblock, it results in FPMCU not
     * working after a S3 resume. This is a known issue.
     */
-	PAD_CFG_GPO(GPP_D1, 0, DEEP),
+	PAD_CFG_OD_GPO(GPP_D1, DEEP),
    /* D2  : ISH_GP2 ==> EN_FP_PWR */
    PAD_CFG_GPO(GPP_D2, 1, DEEP),
    /* D11 : ISH_SPI_MISO ==> EN_PP3300_SSD */
@@ -168,7 +168,7 @@
    PAD_CFG_GPO(GPP_B4, 1, DEEP),

/* D1  : ISH_GP1 ==> FP_RST_ODL */
-	PAD_CFG_GPO(GPP_D1, 0, DEEP),
+	PAD_CFG_OD_GPO(GPP_D1, DEEP),
    /* D2  : ISH_GP2 ==> EN_FP_PWR */
    PAD_CFG_GPO(GPP_D2, 0, DEEP),

diff --git a/src/mainboard/google/brya/variants/brya0/variant.c b/src/mainboard/google/brya/variants/brya0/variant.c
index e9ae51e..0883740 100644
--- a/src/mainboard/google/brya/variants/brya0/variant.c
+++ b/src/mainboard/google/brya/variants/brya0/variant.c
@@ -1,11 +1,21 @@
 /* SPDX-License-Identifier: GPL-2.0-only */

+#include <baseboard/variants.h>
 #include <chip.h>
 #include <fw_config.h>
-#include <baseboard/variants.h>
+#include <gpio.h>

void variant_update_soc_chip_config(struct soc_intel_alderlake_config *config)
 {
    config->cnvi_bt_audio_offload = fw_config_probe(FW_CONFIG(AUDIO,
    						MAX98373_ALC5682_SNDW));
 }
+
+void variant_init(void)
+{
+	/*
+	 * Hold the FP MCU in reset.  This is performed here as there's not a
+	 * macro to initialize a value for an open-drain gpio.
+	 */
+	gpio_od_set(GPP_D1, 0);
+}