[coreboot-gerrit] [S] Change in coreboot[main]: cpu/x86: Conditionally invalidate caches based on self-snooping support

[Subrata Banik (Code Review)]

Subrata Banik has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/87182?usp=email )

Change subject: cpu/x86: Conditionally invalidate caches based on self-snooping support
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cpu/x86: Conditionally invalidate caches based on self-snooping support

The code currently unconditionally flushes or invalidates the entire
cache (using `clflush_region` or `wbinvd`) after loading the SIPI vector
for APs and after loading SMM handlers.

This commit modifies this behavior to only perform these cache
operations if the CPU does *not* support self-snooping.

Rationale:

- Self-snooping CPUs can maintain cache coherency within the core/complex
  more efficiently. CPU with self-snoop enabled does not necessarily need
  to perform wbinvd to ensure data written to the cache is reflected in
  main memory. Self-snooping CPUs employ a write-back caching policy,
  combined with a cache coherence protocol, to manage data writes and
  ensure consistency between cache and main memory.

When the BSP writes the SIPI vector or SMM handlers to memory, other
  units within the same CPU that might be caching these regions should
  be aware of the updates through the self-snooping mechanism. A full
  cache flush or invalidate to ensure cache contains reaches to main
  memory might be unnecessary and could negatively impact performance.

By conditionally performing these cache operations based on
`self_snooping_supported()`, we can optimize the boot process for CPUs
that have advanced cache coherency features while maintaining correct
behavior on older or simpler CPUs.

TEST=Boot google/rex, brox and fatcat with this patch. Able to reduce
boot time by ~19-25ms.

Change-Id: If32439752d0ceaa03b1d81873ea0bc562092e9d5
Signed-off-by: Subrata Banik 
---
M src/cpu/x86/mp_init.c
1 file changed, 12 insertions(+), 8 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/82/87182/1

diff --git a/src/cpu/x86/mp_init.c b/src/cpu/x86/mp_init.c
index 47b3a9e..06ab037 100644
--- a/src/cpu/x86/mp_init.c
+++ b/src/cpu/x86/mp_init.c
@@ -365,12 +365,14 @@
    ap_count = &sp->ap_count;
    atomic_set(ap_count, 0);

-	/* Make sure SIPI data hits RAM so the APs that come up will see the
-	   startup code even if the caches are disabled. */
-	if (clflush_supported())
-		clflush_region((uintptr_t)mod_loc, module_size);
-	else
-		wbinvd();
+	if (!self_snooping_supported()) {
+		/* Make sure SIPI data hits RAM so the APs that come up will see the
+		   startup code even if the caches are disabled. */
+		if (clflush_supported())
+			clflush_region((uintptr_t)mod_loc, module_size);
+		else
+			wbinvd();
+	}

return ap_count;
 }
@@ -826,8 +828,10 @@
    	smm_disable();
    }

-	/* Ensure the SMM handlers hit DRAM before performing first SMI. */
-	wbinvd();
+	if (!self_snooping_supported()) {
+		/* Ensure the SMM handlers hit DRAM before performing first SMI. */
+		wbinvd();
+	}

/*
     * Indicate that the SMM handlers have been loaded and MP