[coreboot-gerrit] Change in coreboot[master]: (TEST ONLY)mb/google/brya/var/vell: Add 5G WWAN ACPI support for vell

[Robert Chen (Code Review)]

Robert Chen has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/62719 )

Change subject: (TEST ONLY)mb/google/brya/var/vell: Add 5G WWAN ACPI support for vell
......................................................................

(TEST ONLY)mb/google/brya/var/vell: Add 5G WWAN ACPI support for vell

Add FM350GL 5G WWAN support using drivers/wwan/fm and addtional PM
features from RTD3.

BUG=b:220084872
TEST=emerge-brya coreboot

Signed-off-by: Robert Chen 
Change-Id: Ica7863b337cd1b55ec3bac771cf9bc774598a95e
---
M src/mainboard/google/brya/Kconfig.name
M src/mainboard/google/brya/variants/vell/gpio.c
M src/mainboard/google/brya/variants/vell/include/variant/gpio.h
M src/mainboard/google/brya/variants/vell/overridetree.cb
4 files changed, 34 insertions(+), 3 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/19/62719/1

diff --git a/src/mainboard/google/brya/Kconfig.name b/src/mainboard/google/brya/Kconfig.name
index 3895aab..dd84075 100644
--- a/src/mainboard/google/brya/Kconfig.name
+++ b/src/mainboard/google/brya/Kconfig.name
@@ -154,10 +154,11 @@
 config BOARD_GOOGLE_VELL
    bool "->  Vell"
    select BOARD_GOOGLE_BASEBOARD_BRYA
+	select CHROMEOS_WIFI_SAR if CHROMEOS
    select DRIVERS_GFX_GENERIC
    select DRIVERS_INTEL_MIPI_CAMERA
+	select HAVE_WWAN_POWER_SEQUENCE
    select SOC_INTEL_COMMON_BLOCK_IPU
-	select CHROMEOS_WIFI_SAR if CHROMEOS

config BOARD_GOOGLE_VOLMAR
    bool "->  Volmar"
diff --git a/src/mainboard/google/brya/variants/vell/gpio.c b/src/mainboard/google/brya/variants/vell/gpio.c
index e6588b9..2fa7ae1 100644
--- a/src/mainboard/google/brya/variants/vell/gpio.c
+++ b/src/mainboard/google/brya/variants/vell/gpio.c
@@ -39,11 +39,17 @@
    PAD_CFG_NF_LOCK(GPP_E12, NONE, NF3, LOCK_CONFIG),
    /* E13 : THC0_SPI1_IO2 ==> UWB_GSPI0_DO */
    PAD_CFG_NF_LOCK(GPP_E13, NONE, NF3, LOCK_CONFIG),
+	/* E16 : RSVD_TP ==> WWAN_RST_L */
+	PAD_CFG_GPO(GPP_E16, 1, DEEP),
    /* E22 : DDPA_CTRLCLK ==> WWAN_CONFIG0 */
    PAD_CFG_GPI(GPP_E22, NONE, DEEP),
    /* E23 : DDPA_CTRLDATA ==> USB_C3_OC_ODL */
    PAD_CFG_NF(GPP_E23, NONE, DEEP, NF1),
-
+	/*
+	 * E0 : SATAXPCIE0 ==> WWAN_PERST_L
+	 * Drive high here, so that PERST_L is sequenced after RST_L
+	 */
+	PAD_CFG_GPO(GPP_E0, 1, DEEP),
    /* F19 : NC */
    PAD_NC(GPP_F19, NONE),

@@ -94,6 +100,8 @@

/* Early pad configuration in bootblock */
 static const struct pad_config early_gpio_table[] = {
+	/* A12 : SATAXPCIE1 ==> EN_PP3300_WWAN */
+	PAD_CFG_GPO(GPP_A12, 1, DEEP),
    /* A13 : PMC_I2C_SCL ==> GSC_PCH_INT_ODL */
    PAD_CFG_GPI_APIC(GPP_A13, NONE, PLTRST, LEVEL, INVERT),
    /* B4  : PROC_GP3 ==> SSD_PERST_L */
@@ -117,7 +125,8 @@
    PAD_CFG_GPO(GPP_D3, 1, DEEP),
    /* D11 : ISH_SPI_MISO ==> USB_C0_LSX_SOC_TX */
    PAD_CFG_NF(GPP_D11, NONE, DEEP, NF4),
-
+	/* E0  : SATAXPCIE0 ==> WWAN_PERST_L (updated in ramstage) */
+	PAD_CFG_GPO(GPP_E0, 0, DEEP),
    /* E3  : PROC_GP0 ==> MEM_STRAP_0 */
    PAD_CFG_GPI(GPP_E3, NONE, DEEP),
    /* E5  : SATA_DEVSLP1 ==> MEM_CH_SEL */
@@ -131,6 +140,8 @@
    PAD_CFG_GPO(GPP_E16, 0, DEEP),
    /* F18 : THC1_SPI2_INT# ==> EC_IN_RW_OD */
    PAD_CFG_GPI(GPP_F18, NONE, DEEP),
+	/* F21 : EXT_PWR_GATE2# ==> WWAN_FCPO_L (updated in romstage) */
+	PAD_CFG_GPO(GPP_F21, 0, DEEP),
    /* H10 : UART0_RXD ==> UART_PCH_RX_DBG_TX */
    PAD_CFG_NF(GPP_H10, NONE, DEEP, NF2),
    /* H11 : UART0_TXD ==> UART_PCH_TX_DBG_RX */
@@ -162,6 +173,8 @@
 static const struct pad_config romstage_gpio_table[] = {
    /* B4  : PROC_GP3 ==> SSD_PERST_L */
    PAD_CFG_GPO(GPP_B4, 1, DEEP),
+	/* F21 : EXT_PWR_GATE2# ==> WWAN_FCPO_L (set here for correct power sequencing) */
+	PAD_CFG_GPO(GPP_F21, 1, DEEP),
 };

const struct pad_config *variant_romstage_gpio_table(size_t *num)
diff --git a/src/mainboard/google/brya/variants/vell/include/variant/gpio.h b/src/mainboard/google/brya/variants/vell/include/variant/gpio.h
index c4fe342..99d09b2 100644
--- a/src/mainboard/google/brya/variants/vell/include/variant/gpio.h
+++ b/src/mainboard/google/brya/variants/vell/include/variant/gpio.h
@@ -5,4 +5,10 @@

#include <baseboard/gpio.h>

+#define WWAN_FCPO	GPP_F21
+#define WWAN_RST	GPP_E16
+#define WWAN_PERST	GPP_E0
+#define T1_OFF_MS	16
+#define T2_OFF_MS	2
+
 #endif
diff --git a/src/mainboard/google/brya/variants/vell/overridetree.cb b/src/mainboard/google/brya/variants/vell/overridetree.cb
index 5f2780e..2f4e4af 100644
--- a/src/mainboard/google/brya/variants/vell/overridetree.cb
+++ b/src/mainboard/google/brya/variants/vell/overridetree.cb
@@ -155,6 +155,17 @@
    			device generic 0 on end
    		end
    	end
+		device ref pcie_rp6 on
+			chip drivers/wwan/fm
+				register "fcpo_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_F21)"
+				register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_E16)"
+				register "perst_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_E0)"
+				register "wake_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_A7)"
+				use rp6_rtd3 as rtd3dev
+				device generic 0 on
+				end
+			end
+		end
    	device ref pcie_rp8 off end
    	device ref pcie_rp9 off end
    	device ref tcss_dma0 on