Attention is currently required from: Angel Pons, Arthur Heymans, Christian Walter, Jincheng Li, Johnny Lin, Jonathan Zhang, Lean Sheng Tan, Patrick Rudolph, Shuo Liu, Tim Chu.
Hello Angel Pons, Arthur Heymans, Christian Walter, Jincheng Li, Johnny Lin, Jonathan Zhang, Lean Sheng Tan, Patrick Rudolph, Tim Chu, build bot (Jenkins),
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/82092?usp=email
to look at the new patch set (#9).
The following approvals got outdated and were removed: Code-Review+2 by Lean Sheng Tan
Change subject: soc/intel/xeon_sp: Add get_cxl_mode ......................................................................
soc/intel/xeon_sp: Add get_cxl_mode
Configuration variable implementation (VPD, et al) is regarded to be mainboard specific and should not be bounded to SoC codes.
Add get_cxl_mode so that SoC codes do not need to get this configuration from VPD any more.
TEST=Build and boot on intel/archercity CRB with no significant log differences
Change-Id: I1e08e92ad769112d7e570ee12cf973451a3befc0 Signed-off-by: Shuo Liu shuo.liu@intel.com Signed-off-by: Jincheng Li jincheng.li@intel.com --- M src/drivers/ocp/include/vpd.h M src/mainboard/intel/archercity_crb/Makefile.mk A src/mainboard/intel/archercity_crb/util.c M src/mainboard/inventec/transformers/Makefile.mk A src/mainboard/inventec/transformers/util.c M src/soc/intel/xeon_sp/include/soc/chip_common.h M src/soc/intel/xeon_sp/include/soc/util.h M src/soc/intel/xeon_sp/spr/romstage.c M src/soc/intel/xeon_sp/uncore.c M src/soc/intel/xeon_sp/util.c 10 files changed, 78 insertions(+), 19 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/92/82092/9