[coreboot-gerrit] Change in coreboot[master]: soc/tigerlake: Fix 16-bit read/write PCI_COMMAND register

[HAOUAS Elyes (Code Review)]

Hello build bot (Jenkins), Patrick Rudolph,

I'd like you to reexamine a change. Please visit

https://review.coreboot.org/c/coreboot/+/40838

to look at the new patch set (#2).

Change subject: soc/tigerlake: Fix 16-bit read/write PCI_COMMAND register
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soc/tigerlake: Fix 16-bit read/write PCI_COMMAND register

Change-Id: I1731313798a4aadcbc17808bfe02b50bf8bd41db
Signed-off-by: Elyes HAOUAS 
---
M src/soc/intel/tigerlake/bootblock/pch.c
M src/soc/intel/tigerlake/graphics.c
2 files changed, 7 insertions(+), 9 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/38/40838/2