Francis Rowe (info@gluglug.org.uk) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/7786
-gerrit
commit 694d592d5ea081ade705f20cae56912866196a8f Author: Francis Rowe info@gluglug.org.uk Date: Fri Dec 12 12:42:01 2014 +0000
northbridge/gm45/raminit.c: enable GS45 high-performance mode
X200S uses GS45 chipset, unlike X200 which uses GM45. These two chipsets are mostly compatible except for raminit.
The datasheets for GS45 describe a high- and low-performance mode for different CPU's. Coreboot currently disables GS45 altogether, but forcing coreboot to treat high-performance GS45 as GM45 makes the X200S boot if it has the right CPU type.
Hardcode-enable GS45 high-performance mode in coreboot, passing it off as GM45. This is known to work with all CPUs except the SU (low performance) models.
Patch courtesy of sgsit.
Change-Id: I57032bb6e1ebdaf4e2aa09548e73d253afb9b078 Signed-off-by: Francis Rowe info@gluglug.org.uk Signed-off-by: Steve Shenton sgsit@libreboot.org --- src/northbridge/intel/gm45/raminit.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/src/northbridge/intel/gm45/raminit.c b/src/northbridge/intel/gm45/raminit.c index 60b05bd..da38ef4 100644 --- a/src/northbridge/intel/gm45/raminit.c +++ b/src/northbridge/intel/gm45/raminit.c @@ -109,8 +109,8 @@ void get_gmch_info(sysinfo_t *sysinfo) printk(BIOS_SPEW, "GMCH: GS40\n"); break; case GMCH_GS45: - printk(BIOS_SPEW, "GMCH: GS45, using low power mode by default\n"); - sysinfo->gs45_low_power_mode = 1; + printk(BIOS_SPEW, "GMCH: GS45, using high performance mode by default\n"); + sysinfo->gs45_low_power_mode = 0; break; case GMCH_PM45: printk(BIOS_SPEW, "GMCH: PM45\n"); @@ -1693,7 +1693,7 @@ void raminit(sysinfo_t *const sysinfo, const int s3resume) { const dimminfo_t *const dimms = sysinfo->dimms; const timings_t *const timings = &sysinfo->selected_timings; - const int sff = sysinfo->gfx_type == GMCH_GS45; + const int sff = (sysinfo->gfx_type == GMCH_GS45) && (sysinfo->gs45_low_power_mode == 1);
int ch; u8 reg8;