[coreboot-gerrit] [S] Change in coreboot[master]: soc/amd/stoneyridge/acpi/sb_pci0_fch: report correct PCI MMIO BAR window

[Felix Held (Code Review)]

Attention is currently required from: Matt DeVillier.

Hello build bot (Jenkins), Matt DeVillier,

I'd like you to reexamine a change. Please visit

https://review.coreboot.org/c/coreboot/+/74809

to look at the new patch set (#2).

Change subject: soc/amd/stoneyridge/acpi/sb_pci0_fch: report correct PCI MMIO BAR window
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soc/amd/stoneyridge/acpi/sb_pci0_fch: report correct PCI MMIO BAR window

This ports back commit commit d75ee46d3ce6 ("soc/amd/picasso/acpi:
Change PCI0 BAR window") to Stoneyridge so that the correct end of the
non-fixed MMIO region gets reported in PCI0's _CRS method.

Signed-off-by: Felix Held 
Change-Id: I19153947cbb1b1b684291765eb1902caac65b9ec
---
M src/soc/amd/stoneyridge/acpi/sb_pci0_fch.asl
1 file changed, 16 insertions(+), 9 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/09/74809/2