Usha P has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/54351 )
Change subject: [TEST]: adln local changes to allign with working recipe ......................................................................
[TEST]: adln local changes to allign with working recipe
This patch has the following changes 1. Chromeos.fmd allignment to 10MB 2. devicetree changes to diable TBT and PEG 3. ASPM for NVME boot 4. Allign FSP UPD with IFWI
Signed-off-by: Usha P usha.p@intel.com Change-Id: Ie87944868bf2d6a1b6b6c1e42f14d5b45b5bda02 --- M src/mainboard/intel/adlrvp/chromeos.fmd M src/mainboard/intel/adlrvp/devicetree.cb M src/soc/intel/alderlake/fsp_params.c M src/soc/intel/alderlake/romstage/fsp_params.c 4 files changed, 55 insertions(+), 53 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/51/54351/1
diff --git a/src/mainboard/intel/adlrvp/chromeos.fmd b/src/mainboard/intel/adlrvp/chromeos.fmd index 5c9ef47..1905fae 100644 --- a/src/mainboard/intel/adlrvp/chromeos.fmd +++ b/src/mainboard/intel/adlrvp/chromeos.fmd @@ -1,48 +1,42 @@ -FLASH 32M { - SI_ALL 6M { - SI_DESC 4K - SI_EC 512K +FLASH@0xfe000001 32M { + SI_ALL@0x0 0x1600000 { + SI_DESC 0x1000 + SI_EC 0x80000 SI_ME } - SI_BIOS 26M { - RW_SECTION_A 8M { - VBLOCK_A 64K - FW_MAIN_A(CBFS) - RW_FWID_A 64 - ME_RW_A(CBFS) 3M + SI_BIOS { + RW_SECTION_A 0x2E8000 { + VBLOCK_A 0x10000 + FW_MAIN_A(CBFS) 0x2d7fc0 + RW_FWID_A 0x40 } - RW_LEGACY(CBFS) 1M - RW_MISC 1M { - UNIFIED_MRC_CACHE(PRESERVE) 192K { - RECOVERY_MRC_CACHE 64K - RW_MRC_CACHE 128K + RW_SECTION_B 0x2E8000 { + VBLOCK_B 0x10000 + FW_MAIN_B(CBFS) 0x2d7fc0 + RW_FWID_B 0x40 + } + RW_MISC 0x30000 { + UNIFIED_MRC_CACHE(PRESERVE) 0x20000 { + RECOVERY_MRC_CACHE 0x10000 + RW_MRC_CACHE 0x10000 } - RW_ELOG(PRESERVE) 16K - RW_SHARED 16K { - SHARED_DATA 8K - VBLOCK_DEV 8K + RW_ELOG(PRESERVE) 0x4000 + RW_SHARED 0x4000 { + SHARED_DATA 0x2000 + VBLOCK_DEV 0x2000 } - RW_VPD(PRESERVE) 8K - RW_NVRAM(PRESERVE) 24K + RW_VPD(PRESERVE) 0x2000 + RW_NVRAM(PRESERVE) 0x6000 } - # This section starts at the 16M boundary in SPI flash. - # ADL does not support a region crossing this boundary, - # because the SPI flash is memory-mapped into two non- - # contiguous windows. - RW_SECTION_B 8M { - VBLOCK_B 64K - FW_MAIN_B(CBFS) - RW_FWID_B 64 - ME_RW_B(CBFS) 3M - } - # Make WP_RO region align with SPI vendor - # memory protected range specification. - WP_RO 8M { - RO_VPD(PRESERVE) 16K + # RW_LEGACY needs to be minimum of 1MB + # RW_LEGACY(CBFS) 0x500000 + WP_RO { + RO_VPD(PRESERVE) 0x4000 RO_SECTION { - FMAP 2K - RO_FRID 64 - GBB@4K 448K + FMAP 0x800 + RO_FRID 0x40 + RO_FRID_PAD 0x7c0 + GBB 0x3000 COREBOOT(CBFS) } } diff --git a/src/mainboard/intel/adlrvp/devicetree.cb b/src/mainboard/intel/adlrvp/devicetree.cb index 23913cc..bdbf1fe1 100644 --- a/src/mainboard/intel/adlrvp/devicetree.cb +++ b/src/mainboard/intel/adlrvp/devicetree.cb @@ -205,7 +205,7 @@
device domain 0 on device pci 00.0 on end # Host Bridge - device pci 01.0 on end # PEG10 + device pci 01.0 off end # PEG10 device pci 02.0 on end # Graphics device pci 04.0 on chip drivers/intel/dptf @@ -302,20 +302,20 @@ device generic 0 on end end end # DPTF - device pci 05.0 on end # IPU - device pci 06.0 on end # PEG60 - device pci 06.2 on end # PEG62 - device pci 07.0 on end # TBT_PCIe0 - device pci 07.1 on end # TBT_PCIe1 - device pci 07.2 on end # TBT_PCIe2 - device pci 07.3 on end # TBT_PCIe3 + device pci 05.0 off end # IPU + device pci 06.0 off end # PEG60 + device pci 06.2 off end # PEG62 + device pci 07.0 off end # TBT_PCIe0 + device pci 07.1 off end # TBT_PCIe1 + device pci 07.2 off end # TBT_PCIe2 + device pci 07.3 off end # TBT_PCIe3 device pci 08.0 off end # GNA - device pci 09.0 off end # NPK + device pci 09.0 on end # NPK device pci 0a.0 off end # Crash-log SRAM - device pci 0d.0 on end # USB xHCI - device pci 0d.1 on end # USB xDCI (OTG) - device pci 0d.2 on end # TBT DMA0 - device pci 0d.3 on end # TBT DMA1 + device pci 0d.0 off end # USB xHCI + device pci 0d.1 off end # USB xDCI (OTG) + device pci 0d.2 off end # TBT DMA0 + device pci 0d.3 off end # TBT DMA1 device pci 0e.0 off end # VMD device pci 10.0 off end device pci 10.1 off end @@ -400,6 +400,6 @@ device pci 1f.4 on end # SMBus device pci 1f.5 on end # SPI device pci 1f.6 off end # GbE - device pci 1f.7 off end # TH + device pci 1f.7 on end # TH end end diff --git a/src/soc/intel/alderlake/fsp_params.c b/src/soc/intel/alderlake/fsp_params.c index 2ab1825..7ed9dd6 100644 --- a/src/soc/intel/alderlake/fsp_params.c +++ b/src/soc/intel/alderlake/fsp_params.c @@ -295,6 +295,7 @@ params->Cx = 1; params->PsOnEnable = 1;
+ memset(params->PcieRpAspm, 0, sizeof(params->PcieRpAspm)); mainboard_silicon_init_params(params); }
diff --git a/src/soc/intel/alderlake/romstage/fsp_params.c b/src/soc/intel/alderlake/romstage/fsp_params.c index ba6e036..fdeb06d 100644 --- a/src/soc/intel/alderlake/romstage/fsp_params.c +++ b/src/soc/intel/alderlake/romstage/fsp_params.c @@ -233,7 +233,7 @@ /* Skip CPU replacement check */ m_cfg->SkipCpuReplacementCheck = !config->CpuReplacementCheck;
- m_cfg->TmeEnable = CONFIG(INTEL_TME); + m_cfg->TmeEnable = 0x0;
/* Skip GPIO configuration from FSP */ m_cfg->GpioOverride = 0x1; @@ -243,6 +243,13 @@ m_cfg->CpuCrashLogDevice = 1; m_cfg->CpuCrashLogEnable = 1; } + + m_cfg->LpDdrDqDqsReTraining = 0; + m_cfg->DmiMaxLinkSpeed = 0x4; + m_cfg->EnableC6Dram = 0x1; + m_cfg->DdrFreqLimit = 2133; + m_cfg->WrcFeatureEnable = 0x0; + }
void platform_fsp_memory_init_params_cb(FSPM_UPD *mupd, uint32_t version)