Attention is currently required from: Jason Glenesk, Raul Rangel, Martin Roth, Fred Reitberger, Felix Held.
Hello build bot (Jenkins), Jason Glenesk, Raul Rangel, Fred Reitberger, Felix Held,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/74288
to look at the new patch set (#2).
Change subject: soc/amd/common/blk/pcie: Program LTR max latencies ......................................................................
soc/amd/common/blk/pcie: Program LTR max latencies
PCIe bridges need to provide the LTR (latency tolernace reporting) maximum snoop/non-snoop values so that they are inherited by downstream PCIe devices which support and enable LTR. Without this, downstream devices cannot have LTR enabled, which is a requirement for supporting PCIe L1 substates. Enabling L1ss without LTR has unpredictable behavior, including some devices refusing to enter L1 low power modes at all.
Program the max snoop/non-snoop latency values for all PCIe bridges using the same value used by AGESA/FSP, 1.047ms.
BUG=b:265890321 TEST=build/boot google/skyrim (multiple variants, NVMe drives), ensure LTR is enabled, latency values are correctly set, and that device power draw at idle is in the expected range (<25 mW).
Change-Id: Icf188e69cf5676be870873c56d175423d16704b4 Signed-off-by: Matt DeVillier matt.devillier@amd.corp-partner.google.com --- M src/soc/amd/common/block/pci/pcie_gpp.c 1 file changed, 40 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/88/74288/2