Attention is currently required from: Angel Pons, Arthur Heymans, Chen, Gang C, Christian Walter, Jincheng Li, Johnny Lin, Jonathan Zhang, Lean Sheng Tan, Patrick Rudolph, Shuo Liu, Tim Chu.
Hello Angel Pons, Arthur Heymans, Chen, Gang C, Christian Walter, Jincheng Li, Johnny Lin, Jonathan Zhang, Lean Sheng Tan, Patrick Rudolph, Tim Chu, build bot (Jenkins),
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/82090?usp=email
to look at the new patch set (#8).
The following approvals got outdated and were removed: Code-Review+2 by Angel Pons, Verified+1 by build bot (Jenkins)
The change is no longer submittable: Code-Review and Verified are unsatisfied now.
Change subject: soc/intel/xeon_sp: Move VPD based settings to mainboard codes ......................................................................
soc/intel/xeon_sp: Move VPD based settings to mainboard codes
Configuration variable implementation (VPD, et al) is regarded to be mainboard specific and should not be bounded to SoC codes.
This patch moves the VPD based settings (FSP log level, et al) from SoC codes to mainboard codes.
TEST=Build and boot on intel/archercity CRB with no significant log differences
Change-Id: Iefea72eec6e52f8d1ae2d10e1edbabdebf4dff91 Signed-off-by: Shuo Liu shuo.liu@intel.com Signed-off-by: Jincheng Li jincheng.li@intel.com --- M src/mainboard/intel/archercity_crb/romstage.c M src/mainboard/inventec/transformers/romstage.c M src/soc/intel/xeon_sp/spr/romstage.c 3 files changed, 33 insertions(+), 85 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/90/82090/8